Buried power rails located in a base layer including first, second, and third etch stop layers
Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.
1. An integrated chip, comprising:
a frontside device above a base layer, having a channel and source/drain structures;
a buried power rail in the base layer, underneath the frontside device; and
an electrical contact that makes an electrical connection between the buried power rail and the frontside device,
wherein the base layer includes:
a first etch stop layer, which the buried power rail penetrates;
a first semiconductor layer between the first etch stop layer and the frontside device;
a second etch stop layer, between the first semiconductor layer and the frontside device;
a second semiconductor layer between the second etch stop layer and the frontside device; and
a third etch stop layer between the second semiconductor layer and the frontside device.
2. The integrated chip of claim 1 , further comprising a backside power distribution network that includes an interconnect that makes electrical contact with the buried power rail.
3. The integrated chip of claim 1 , wherein the buried power rail is wider at a back surface of the base layer than where the electrical contact makes the electrical connection with the buried power rail.
4. An integrated chip, comprising:
a plurality of frontside devices above a base layer, each having a channel and source/drain structures, and having an inter-device distance between an adjacent pair of frontside devices of the plurality of frontside devices;
a buried power rail in the base layer, underneath the pair of frontside devices, having a width that is greater than the inter-device distance; and
an electrical contact that makes an electrical connection between the buried power rail and one of the pair of frontside devices,
wherein the base layer includes:
a first etch stop laver, which the buried power rail penetrates;
a first semiconductor layer between the first etch stop layer and the one of the pair of frontside devices;
a second etch stop layer, between the first semiconductor layer and the one of the pair of frontside devices;
a second semiconductor layer between the second etch stop layer and the one of the pair of frontside devices; and
a third etch stop layer between the second semiconductor layer and the one of the pair of frontside devices.
5. The integrated chip of claim 4 , further comprising a backside power distribution network that includes an interconnect that makes electrical contact with the buried power rail.
6. The integrated chip of claim 4 , wherein the buried power rail is wider at a back surface of the base layer than where the electrical contact makes the electrical connection with the buried power rail.