High voltage electrostatic devices
The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.
1. A structure comprising a high voltage NPN with polysilicon material bounded by silicide block layers located at collector and emitter regions, the polysilicon material being on an isolation structure located in a base region, the isolation structure extending between a collector and an emitter within a substrate, the polysilicon material extending to at least one of the collector and the emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT and an epitaxial semiconductor material between the collector and the base region.
2. The structure of claim 1 , wherein the isolation structure extends between wells connected to an anode and a cathode.
3. The structure of claim 2 , further comprising an n-type area of a field transistor under the isolation structure.
4. The structure of claim 3 , further comprising a p-dopant well under the isolation structure.
5. The structure of claim 4 , wherein the polysilicon material is exclusively on the isolation structure.
6. The structure of claim 1 , further comprising a resistor-capacitor (RC) circuit connecting to the polysilicon material.
7. The structure of claim 6 , wherein the RC circuit comprises a resistor connected to a cathode of the high voltage NPN.
8. The structure of claim 6 , wherein the RC circuit comprises a high voltage alternate polarity metal-oxide-metal (HV APMOM) capacitor connected to an anode of the high voltage NPN.
9. The structure of claim 6 , further comprising a silicon controlled rectifier (SCR) comprising an NPN structure under an anode in an insulator material, the anode connected to the RC circuit.
10. The structure of claim 1 , further comprising a substrate isolated from remaining portions of the high voltage NPN by an n+ buried layer.
11. A structure comprising a silicon controlled rectifier (SCR) and a polysilicon material bounded by silicide block layers located at collector and emitter regions, the polysilicon material being on an isolation structure located within a base region, the isolation structure extending between a collector and an emitter within a substrate, the polysilicon material extending to at least one of the collector and the emitter of a bipolar junction transistor (BJT), the polysilicon material completely covering the base region of the BJT, and the SCR is under an anode in an insulator material and the SCR contacting the isolation structure and an epitaxial semiconductor material between the collector and the base region.
12. The structure of claim 11 , wherein the isolation structure comprises one of a shallow trench isolation (STI) structure and a local oxidation of silicon (LOCOS) structure.
13. The structure of claim 12 , further comprising a p-type area of a field transistor which is under the isolation structure.
14. The structure of claim 13 , further comprising an n-dopant well under the isolation structure.
15. The structure of claim 14 , further comprising a high voltage NPN under the anode in the insulator material.
16. The structure of claim 11 , further comprising a resistor-capacitor (RC) circuit which is connected to the polysilicon material.
17. The structure of claim 16 , wherein the RC circuit comprises a resistor connected to a cathode of the SCR.
18. The structure of claim 16 , wherein the RC circuit comprises a high voltage alternate polarity metal-oxide-metal (HV APMOM) capacitor connected to the anode.
19. The structure of claim 11 , further comprising a substrate isolated from remaining portions of the SCR by an n+ buried layer (NBL).
20. A method, comprising:
forming an electrostatic high voltage device with a single polysilicon material bounded by silicide block layers located at collector and emitter regions, the single polysilicon material being on an isolation structure, the isolation structure being in a base region and extending between a collector and an emitter within a substrate;
forming a bipolar junction transistor (BJT) in the base region which is completely covered by the single polysilicon material and an epitaxial semiconductor material between a collector of the BJT and the base region; and
forming a buried layer which isolates the electrostatic high voltage device from a substrate.