IP Library › Granted Patent US 11,990,474
Granted Patent B2
US 11,990,474 · App. 18/151,990 · Granted May 21, 2024

Method of making a semiconductor device

Inventors: Shu Fang Fu (Hsinchu, TW); Chi-Feng Huang (Hsinchu, TW); Chia-Chung Chen (Hsinchu, TW); Victor Chiang Liang (Hsinchu, TW); Fu-Huan Tsai (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L27/0886H01L21/823807H01L21/823821H01L21/823871H01L21/823878H01L27/0207H01L27/092H01L27/0924H01L29/1041H01L29/7835H01L29/785H01L21/823814H03K3/0315
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Quick Facts
Patent No.
US 11,990,474
App. No.
18/151,990
Granted
May 21, 2024
Kind
B2
Abstract

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Claims (34)

1. A method of fabricating a semiconductor device, the method comprising:

forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip;

forming a first source/drain feature between the gate structure and the first edge structure;

forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature; and

implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

2. The method of claim 1 , wherein implanting the buried channel comprises implanting dopants to define a top surface of the buried channel a distance of about 2 nanometers (nm) to about 7 nm below the top-most surface of the semiconductor strip.

3. The method of claim 1 , wherein implanting the buried channel comprises implanting the buried channel across less than an entire width of the semiconductor strip.

4. The method of claim 1 , further comprising:

forming a first contact over the first source/drain feature; and

forming a second contact over the second source/drain feature, wherein a top-most surface of the first contact is coplanar with a top-most surface of the second contact.

5. The method of claim 4 , further comprising forming a gate contact over the gate structure, wherein a top-most surface of the gate contact is coplanar with the top-most surface of the first contact.

6. The method of claim 1 , wherein forming the first edge structure comprises forming the first edge structure partially over an isolation feature.

7. The method of claim 1 , wherein forming the first source/drain feature comprises forming the first source/drain feature extending above the top-most surface of the semiconductor strip.

8. The method of claim 1 , wherein forming the second source/drain feature comprises forming the second source/drain feature about 1.5 to about 4.5 times farther from the gate structure than the first source/drain feature is from the gate structure.

9. A method of fabricating a semiconductor device, the method comprising:

forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip;

forming a first source/drain feature between the gate structure and a first edge of the semiconductor strip;

forming a second source/drain feature between the gate structure and a second edge of the semiconductor strip, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature; and

implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and an entirety of the buried channel is between the first source/drain feature and the second source/drain feature.

10. The method of claim 9 , wherein at least one of forming the first source/drain feature or forming the second source/drain feature comprises using an epitaxial process.

11. The method of claim 9 , wherein forming the first source/drain feature comprises forming the first source/drain feature extending above a top surface of the semiconductor strip.

12. The method of claim 9 , further comprising forming an isolation feature adjacent to the semiconductor strip.

13. The method of claim 12 , wherein forming the first edge structure comprises forming the first edge structure overlapping the isolation feature.

14. The method of claim 9 , wherein forming the first source/drain feature comprises forming the first source/drain feature a first distance from the first edge structure.

15. The method of claim 14 , wherein forming the second source/drain feature comprises forming the second source/drain feature the first distance from the second edge structure.

16. A method of fabricating a semiconductor device, the method comprising:

forming a gate structure on a semiconductor strip;

forming a first source/drain feature between the gate structure and the first edge structure;

forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature; and

implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

17. The method of claim 16 , wherein implanting the buried channel comprises implanting the buried channel offset from a periphery of the semiconductor strip by a first distance.

18. The method of claim 17 , wherein the first distance ranges from about 2 nanometers (nm) to about 7 nm.

19. The method of claim 17 , wherein implanting the buried channel comprises implanting the buried channel the first distance below the top-most surface of the semiconductor strip.

20. The method of claim 16 , wherein forming the second source/drain feature comprises forming the second source/drain feature to define a ratio between the distance between the gate structure and the first source/drain region to the distance between the gate structure and the second source drain region ranging from about 1.5 to about 4.5.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2023
From: FU, SHU FANG; HUANG, CHI-FENG; CHEN, CHIA-CHUNG; LIANG, VICTOR CHIANG; TSAI, FU-HUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 062317/0332 →
Continuity (5)
Division 16938528 · Jul 24, 2020
Continuation 16586273 · Sep 27, 2019
Division 15255370 · Sep 2, 2016
Provisional Application 62343735 · May 31, 2016
Related Publication 20230163125A1 · May 25, 2023
Cited By (2)
US 12,310,046 US 12,710,588