DRAM circuitry and method of forming DRAM circuitry

1. DRAM circuitry comprising:

a memory array comprising memory cells individually comprising a transistor and a charge-storage device, the transistors individually comprising two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array, one of the source/drain regions being electrically coupled to one of the charge-storage devices, the other of the source/drain regions being electrically coupled to one of multiple sense lines of the memory array;

peripheral circuitry comprising wordline-driver transistors having gates which individually comprise one of the wordlines and comprising sense-line-amplifier transistors having gates which individually comprise one of the sense lines;

the sense-line-amplifier transistors and the wordline-driver transistors individually being a finFET having at least one fin comprising a channel region of the respective finFET, the sense-line-amplifier transistors and the wordline-driver transistors individually comprising two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section; and

the finFETs of the sense-line-amplifer transistors and the finFETs of the wordline-driver transistors individually have two and only two channel-region fins along a vertical line through the individual finFET gate and that bisects channel length of the individual finFET.

2. The DRAM circuitry of claim 1 wherein the conductively-doped epitaxial semiconductor material of the source/drain regions of the sense-line-amplifier transistors have a bottom-most surface that is lower than an uppermost surface of the at least one fin.

3. DRAM circuitry comprising:

a memory array comprising memory cells individually comprising a transistor and a charge-storage device, the transistors individually comprising two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array, one of the source/drain regions being electrically coupled to one of the charge-storage devices, the other of the source/drain regions being electrically coupled to one of multiple sense lines of the memory array;

peripheral circuitry comprising wordline-driver transistors having gates which individually comprise one of the wordlines and comprising sense-line-amplifier transistors having gates which individually comprise one of the sense lines;

the sense-line-amplifier transistors and the wordline-driver transistors individually being a finFET having at least one fin comprising a channel region of the respective finFET, the sense-line-amplifier transistors and the wordline-driver transistors individually comprising two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section; and

the sense-line-amplifier transistors collectively comprise NMOS transistors and PMOS transistors.

4. The DRAM circuitry of claim 3 wherein the source/drain regions of the sense-line-amplifier transistors that comprise conductively-doped epitaxial semiconductor material of the NMOS transistors individually comprise silicon that is conductively-doped with phosphorus.

5. The DRAM circuitry of claim 3 wherein the source/drain regions of the sense-line-amplifier transistors that comprise conductively-doped epitaxial semiconductor material of the PMOS transistors individually comprise a mixture of silicon and germanium that is conductively-doped with boron.

6. DRAM circuitry comprising:

a memory array comprising memory cells individually comprising a transistor and a charge-storage device, the transistors individually comprising two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array, one of the source/drain regions being electrically coupled to one of the charge-storage devices, the other of the source/drain regions being electrically coupled to one of multiple sense lines of the memory array;

peripheral circuitry comprising wordline-driver transistors having gates which individually comprise one of the wordlines and comprising sense-line-amplifier transistors having gates which individually comprise one of the sense lines;

the sense-line-amplifier transistors and the wordline-driver transistors individually being a finFET having at least one fin comprising a channel region of the respective finFET, the sense-line-amplifier transistors and the wordline-driver transistors individually comprising two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section; and

the conductively-doped epitaxial semiconductor material of the source/drain regions of the wordline-driver transistors have a lower surface that is at the same elevation as an uppermost surface of the at least one fin.

7. The DRAM circuitry of claim 6 wherein the conductively-doped epitaxial semiconductor material of the source/drain regions of the sense-line-amplifier transistors have a bottom-most surface that is lower than the uppermost surface of the at least one fin.

8. DRAM circuitry comprising:

a memory array comprising memory cells individually comprising a transistor and a charge-storage device, the transistors individually comprising two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array, one of the source/drain regions being electrically coupled to one of the charge-storage devices, the other of the source/drain regions being electrically coupled to one of multiple sense lines of the memory array;

peripheral circuitry comprising wordline-driver transistors having gates which individually comprise one of the wordlines and comprising sense-line-amplifier transistors having gates which individually comprise one of the sense lines;

the sense-line-amplifier transistors and the wordline-driver transistors individually being a finFET having at least one fin comprising a channel region of the respective finFET, the sense-line-amplifier transistors and the wordline-driver transistors individually comprising two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section; and

comprising gate insulator between the at least one fin and the gates of the sense-line-amplifier transistors and the wordline-driver transistors, the gate insulator that is between the at least one fin and the gates of the sense-line-amplifier transistors being thinner than the gate insulator that is between the at least one fin and the gates of the wordline-driver transistors.

9. The DRAM circuitry of claim 8 wherein the sense-line-amplifier transistors collectively comprise NMOS transistors and PMOS transistors.

10. The DRAM circuitry of claim 8 wherein the gate insulator that is between the at least one fin and the gates of the sense-line-amplifier transistors and the gate insulator that is between the at least one fin and the gates of the wordline-driver transistors are of the same composition relative one another.

11. The DRAM circuitry of claim 10 wherein the same composition is silicon dioxide.

12. The DRAM circuitry of claim 10 wherein the gate insulator that is between the at least one fin and the gates of the sense-line-amplifier transistors has thickness of 5 Angstroms to 30 Angstroms and the gate insulator that is between the at least one fin and the gates of the wordline-driver transistors has thickness of 30 Angstroms to 60 Angstroms.

13. DRAM circuitry comprising:

a memory array comprising memory cells individually comprising a transistor and a charge-storage device, the transistors individually comprising two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array, one of the source/drain regions being electrically coupled to one of the charge-storage devices, the other of the source/drain regions being electrically coupled to one of multiple sense lines of the memory array;

peripheral circuitry comprising wordline-driver transistors having gates which individually comprise one of the wordlines and comprising sense-line-amplifier transistors having gates which individually comprise one of the sense lines;

the sense-line-amplifier transistors and the wordline-driver transistors individually being a finFET having at least one fin comprising a channel region of the respective finFET, the sense-line-amplifier transistors and the wordline-driver transistors individually comprising two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section;

the conductively-doped epitaxial semiconductor material of the source/drain regions of the sense-line-amplifier transistors having a bottom-most surface that is lower than an uppermost surface of the at least one fin;

the conductively-doped epitaxial semiconductor material of the source/drain regions of the wordline-driver transistors having a lower surface that is at the same elevation as the uppermost surface of the at least one fin;

gate insulator between the at least one fin and the gates of the sense-line-amplifier transistors and the wordline-driver transistors, the gate insulator that is between the at least one fin and the gates of the sense-line-amplifier transistors and the gate insulator that is between the at least one fin and the gates of the wordline-driver transistors being of the same composition relative one another, the gate insulator that is between the at least one fin and the gates of the sense-line-amplifier transistors being thinner than the gate insulator that is between the at least one fin and the gates of the wordline-driver transistors.

14. The DRAM circuitry of claim 13 wherein the same composition is silicon dioxide.

15. The DRAM circuitry of claim 13 wherein the gate insulator that is between the at least one fin and the gates of the sense-line-amplifier transistors has thickness of 5 Angstroms to 30 Angstroms and the gate insulator that is between the at least one fin and the gates of the wordline-driver transistors has thickness of 30 Angstroms to 60 Angstroms.

16. The DRAM circuitry of claim 13 wherein the sense-line-amplifier transistors collectively comprise NMOS transistors and PMOS transistors.

17. The DRAM circuitry of claim 16 wherein,

the source/drain regions of the sense-line-amplifier transistors that comprise conductively-doped epitaxial semiconductor material of the NMOS transistors individually comprise silicon that is conductively-doped with phosphorus; and

the source/drain regions of the sense-line-amplifier transistors that comprise conductively-doped epitaxial semiconductor material of the PMOS transistors individually comprise a mixture of silicon and germanium that is conductively-doped with boron.