IP Library Granted Patent US 11,994,571
Granted Patent B2
US 11,994,571 · App. 17/676,340 · Granted May 28, 2024

5-PS-resolution waveform-capture-device on a field-programmable gate-array with dynamic phase-shifting

Inventors: Noeloikeau Charlot (Columbus, OH); Daniel Gauthier (Columbus, OH); Andrew Pomerance (Alexandria, VA)
Assignees: Ohio State Innovation Foundation; Potomac Research LLC
G01R35/005G01R13/02G04F10/005H03K19/173
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Quick Facts
Patent No.
US 11,994,571
App. No.
17/676,340
Granted
May 28, 2024
Kind
B2
Abstract

A waveform capture device (WCD) is a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD may be implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It may be calibrated via a dynamic phase-shifting (DPS) method that requires substantially less data and resources than conventional techniques.

Claims (27)

1. A device comprising:

a time-to-digital converter (TDC); and

a digital oscilloscope (DO),

wherein the device is a waveform-capture-device (WCD), and

wherein the WCD uses a plurality of carry-chains (CCs) to capture a digital waveform without encoding the digital waveform.

2. The device of claim 1 , further comprising a tapped delay line (TDL) comprising a plurality of registers and the plurality of CCs.

3. The device of claim 1 , wherein the WCD is a 5 ps-resolution TDC/ultra-fast DO hybrid.

4. The device of claim 1 , wherein the WCD is implemented on a field-programmable gate-array (FPGA).

5. The device of claim 1 , wherein the WCD is configured to measure complex GHz frequency waveforms at picosecond time intervals.

6. The device of claim 1 , wherein the WCD is calibrated via a dynamic phase-shifting (DPS) process that adjusts a phase of a stable on-board clock.

7. The device of claim 2 , wherein each CC is used to buffer an input signal and wherein the registers are used to capture a waveform of the input signal on an edge of a clock.

8. The device of claim 7 , wherein each CC comprises at least one carry-element (CE) that passes the input signal to another CE after a time-delay.

9. A method of calibrating a waveform-capture-device (WCD), the method comprising using dynamic phase shifting (DPS) for discrete measurement,

wherein the DPS uses dynamic-phase calibration (DPC), and

wherein the DPS generates ps-scale time-intervals without reconfiguring a field-programmable gate-array (FPGA).

10. The method of claim 9 , wherein the DPS functions by adjusting the phase of a stable on-board clock, wherein the clock is a phase-lock loop (PLL).

11. The method of claim 9 , wherein the WCD is a digital buffer and the DPC is a velocity calculation that measures the distance travelled down the digital buffer after a phase-shift.

12. The method of claim 9 , wherein for the discrete measurement, a capture time is incrementally delayed in discrete intervals via the DPS, and an input signal is repeatedly generated and measured once after every accumulated phase shift, thereby allowing for calibration of a carry speed.

13. A waveform-capture-device (WCD) comprising:

a time-to-digital converter (TDC);

a digital oscilloscope (DO); and

a tapped delay line (TDL) comprising a plurality of registers and a plurality of carry-chains (CCs),

wherein the CCs are configured to capture a digital waveform without encoding the digital waveform,

wherein each CC is used to buffer an input signal and wherein the registers are used to capture a waveform of the input signal on an edge of a clock, and

wherein each CC comprises at least one carry-element (CD) that passes the input signal to another CE after a time-delay.

14. The device of claim 13 , wherein the WCD is implemented on a field-programmable gate-array (FPGA), wherein the WCD is configured to measure complex GHz frequency waveforms at picosecond time intervals, and wherein the WCD is calibrated via a dynamic phase-shifting (DPS) process that adjusts a phase of a stable on-board clock.

15. The device of claim 14 , wherein the DPS uses dynamic-phase calibration (DPC) and wherein the DPS functions by adjusting the phase of a stable on-board clock, wherein the clock is a phase-lock loop (PLL).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2024
From: CHARLOT, NOELOIKEAU; GAUTHIER, DANIEL
To: OHIO STATE INNOVATION FOUNDATION
Reel/Frame 066467/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2024
From: POMERANCE, ANDREW JOSEPH
To: POTOMAC RESEARCH LLC
Reel/Frame 066467/0375 →
Continuity (2)
Provisional Application 63177435 · Apr 21, 2021
Related Publication 20220342023A1 · Oct 27, 2022