Display device
A display device includes a display panel including pixels coupled to a first scan line and a data line, a power supply to supply voltages, a scan driver to provide a first scan signal to the first scan line a plurality of times for a first frame period (FFP), a data driver to supply a data signal to the data line, and a timing controller to control driving of components. The FFP includes: a first active period (FAP), in which the data signal is supplied; and a first blank period (FBP), in which the data signal is not supplied. The power supply provides on-bias power having a first voltage level (FVL) in the FAP, and provides on-bias power having a second voltage level (SVL) in the FBP. The FBP following the FAP includes a first dimming period in which the on-bias power gradually changes from the FVL to the SVL.
1. A pixel, comprising:
a light-emitting element;
a first transistor coupled between a first node and a second node and including a gate electrode connected to a third node;
a second transistor coupled between a data line and the first node and including a gate electrode connected to a fourth scan line; and
a fourth transistor including a gate electrode connected to a first scan line and configured to be turned on in response to a scan signal supplied to the first scan line to apply a voltage of on-bias power to the first transistor,
wherein a first frame period comprises a first active period and a first blank period following the first active period and comprising a first dimming period, and
wherein the voltage level of the on-bias power gradually increases in the first dimming period.
2. The pixel according to claim 1 , wherein:
the voltage level of the on-bias power is higher in the first blank period than in the first active period.
3. The pixel according to claim 2 , wherein:
the first frame period further comprises a second blank period following the first blank period; and
the voltage level of the on-bias power is higher in the second blank period than in the first blank period.
4. The pixel according to claim 3 , wherein:
second blank period comprises a second dimming period; and
the voltage level of the on-bias power gradually increases in the second dimming period.
5. The pixel according to claim 1 , wherein:
a second frame period comprises a second active period following the first blank period; and
the voltage level of the on-bias power is lower in the second active period than in the first blank period.
6. The pixel according to claim 5 , wherein:
the second active period comprises a second dimming period; and
the voltage level of the on-bias power gradually decreases in the second dimming period.
7. The pixel according to claim 1 , wherein:
a first frame period comprises a first active period;
a second frame period comprises a second active period following the first active period; and
the voltage level of the on-bias power is lower in the second active period than in the first active period.
8. The pixel according to claim 7 , wherein:
the second active period comprises the first dimming period; and
the voltage level of the on-bias power gradually decreases in the first dimming period.
9. The pixel according to claim 1 , wherein the pixel further comprises:
a third transistor coupled between the second node and the third node and including a gate electrode connected to a second scan line;
a fifth transistor coupled between the first node and driving power and including a gate electrode connected to an emission control line;
a sixth transistor coupled between the second node and a fourth node and including a gate electrode connected to the emission control line;
a seventh transistor coupled between the third node and first initialization power and including a gate electrode connected to a third scan line; and
an eighth transistor coupled between the fourth node and second initialization power and including a gate electrode connected to the first scan line,
wherein the fourth transistor is coupled between the first node and the on-bias power.
10. The pixel according to claim 1 , wherein the pixel further comprises:
a third transistor coupled between the second node and the third node and including a gate electrode connected to a second scan line;
a fifth transistor coupled between the first node and driving power and including a gate electrode connected to an emission control line;
a sixth transistor coupled between the second node and a fourth node and including a gate electrode connected to the emission control line;
a seventh transistor coupled between the third node and first initialization power and including a gate electrode connected to a third scan line; and
an eighth transistor coupled between the fourth node and second initialization power and including a gate electrode connected to the first scan line,
wherein the fourth transistor is coupled between the second node and the on-bias power.
11. A pixel, comprising:
a light-emitting element;
a first transistor coupled between a first node and a second node and including a gate electrode connected to a third node;
a second transistor coupled between a data line and the first node and including a gate electrode connected to a fourth scan line; and
an eighth transistor coupled between a fourth node and second initialization power and including a gate electrode connected to a first scan line,
wherein a first frame period comprises a first active period and a first blank period following the first active period and comprising a first dimming period, and
wherein the voltage level of the second initialization power gradually decreases in the first dimming period.
12. The pixel according to claim 11 , wherein:
the voltage level of the second initialization power is lower in the first blank period than in the first active period.
13. The pixel according to claim 12 , wherein:
the first frame period further comprises a second blank period following the first blank period; and
the voltage level of the second initialization power is lower in the second blank period than in the first blank period.
14. The pixel according to claim 13 , wherein:
second blank period comprises a second dimming period; and
the voltage level of the second initialization power gradually decreases in the second dimming period.
15. The pixel according to claim 11 , wherein:
a second frame period comprises a second active period following the first blank period; and
the voltage level of the second initialization power is higher in the second active period than in the first blank period.
16. The pixel according to claim 15 , wherein:
the second active period comprises a second dimming period; and
the voltage level of the second initialization power gradually increases in the second dimming period.
17. The pixel according to claim 11 , wherein:
a first frame period comprises a first active period;
a second frame period comprises a second active period following the first active period; and
the voltage level of the second initialization power is higher in the second active period than in the first active period.
18. The pixel according to claim 17 , wherein:
the second active period comprises the first dimming period; and
the voltage level of the second initialization power gradually increases in the first dimming period.
19. The pixel according to claim 11 , wherein the pixel further comprises:
a third transistor coupled between the second node and the third node and including a gate electrode connected to a second scan line;
a fourth transistor coupled between the first node and on-bias power and including a gate electrode connected to the first scan line;
a fifth transistor coupled between the first node and driving power and including a gate electrode connected to an emission control line;
a sixth transistor coupled between the second node and a fourth node and including a gate electrode connected to the emission control line; and
a seventh transistor coupled between the third node and first initialization power and including a gate electrode connected to a third scan line.
20. The pixel according to claim 11 , wherein the pixel further comprises:
a third transistor coupled between the second node and the third node and including a gate electrode connected to a second scan line;
a fourth transistor coupled between the second node and on-bias power and including a gate electrode connected to the first scan line;
a fifth transistor coupled between the first node and driving power and including a gate electrode connected to an emission control line;
a sixth transistor coupled between the second node and a fourth node and including a gate electrode connected to the emission control line; and
a seventh transistor coupled between the third node and first initialization power and including a gate electrode connected to a third scan line.