Display device and driving circuit

1. A display device, comprising:

a display panel having a plurality of subpixels;

a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, and output a feedback voltage;

a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines;

a power management circuit configured to:

supply a plurality of driving voltages to the gate driving circuit and the data driving circuit, and

supply a compensating high-potential gate voltage to the gate driving circuit based on the feedback voltage transferred from the gate driving circuit; and

a timing controller configured to control the gate driving circuit, the data driving circuit, and the power management circuit,

wherein the power management circuit includes:

a gate sensing switch configured to control a connection between nodes to which the compensating high-potential gate voltage is supplied;

a display sensing switch configured to control a connection between nodes to which a display driving reference voltage is supplied; and

an amplifier configured to supply the compensating high-potential gate voltage or the display driving reference voltage to the data driving circuit according to a control of the gate sensing switch and the display sensing switch.

2. The display device of claim 1 , wherein the gate driving circuit includes a plurality of gate driving integrated circuits, and

wherein at least one of the plurality of gate driving integrated circuits is configured as a feedback gate driving integrated circuit including a feedback circuit for outputting the feedback voltage.

3. The display device of claim 2 , wherein the feedback gate driving integrated circuit is disposed in a corner of the display panel.

4. The display device of claim 2 , wherein the feedback gate driving integrated circuit includes:

a Q node stabilization unit comprising a first transistor and a second transistor, and a QB node connecting a first gate of the first transistor to a second gate of the second transistor,

wherein the feedback circuit is connected to an output of the QB node.

5. The display device of claim 4 , wherein the feedback circuit includes:

at least two feedback transistors having gates connected jointly to the output of the QB node and source nodes connected jointly to a feedback line for transferring the feedback voltage.

6. The display device of claim 2 , wherein the gate driving integrated circuit includes:

a line selection unit configured to charge an M node based on a previous carry signal in response to an input of a line sensing preparation signal;

a Q node control unit configured to charge a Q node to a level of a first high-potential gate voltage in response to the previous carry signal and discharge the Q node to a level of a third low-potential gate voltage in response to an input of a subsequent carry signal;

a Q node stabilization unit configured to discharge the Q node and a QH node to the level of the third low-potential gate voltage in response to a voltage of a QB node;

an inverter unit configured to change a voltage level of the QB node according to a voltage level of the Q node;

a QB node stabilization unit configured to discharge the QB node to the level of the third low-potential gate voltage in response to the subsequent carry signal, a reset signal, and the charging voltage of the M node;

a carry signal output unit configured to output a current carry signal based on a voltage level of a carry clock signal or the level of the third low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node; and

a scan signal output unit configured to output a plurality of scan signals based on voltage levels of a plurality of scan clock signals or a level of a first low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node.

7. The display device of claim 6 , wherein the compensating high-potential gate voltage corresponds to a second high-potential gate voltage driving the inverter unit.

8. The display device of claim 6 , wherein the feedback circuit includes at least one feedback transistor having a gate node connected to the QB node, a drain node connected to a node for supplying the first low-potential gate voltage, and a source node connected to a feedback line for transferring the feedback voltage.

9. The display device of claim 2 , wherein the power management circuit includes a high-potential gate voltage compensation circuit configured to supply the compensating high-potential gate voltage to the plurality of gate driving integrated circuits based on the feedback voltage output by the feedback circuit.

10. The display device of claim 9 , wherein the high-potential gate voltage compensation circuit includes:

an amplifier having a non-inverting input terminal to which the feedback voltage is applied;

a reference resistor connected to an inverting input terminal of the amplifier to transfer a reference voltage;

at least one setting resistor connected to the non-inverting input terminal of the amplifier to transfer at least one setting voltage; and

a feedback resistor connected between the inverting input terminal and an output terminal of the amplifier.

11. The display device of claim 9 , wherein the high-potential gate voltage compensation circuit further includes a scaler configured to change a level of the compensating high-potential gate voltage.

12. The display device of claim 2 , wherein the data driving circuit includes:

an analog-to-digital converter configured to sense a voltage of a sensing line and convert the voltage into digital data;

a characteristic value sensing switch configured to control a connection between the sensing line and a node to which a sensing reference voltage is supplied;

a gate sensing switch configured to control a connection between the sensing line and a node to which the compensating high-potential gate voltage is supplied; and

a sampling switch configured to control a connection between the sensing line and the analog-to-digital converter.

13. The display device of claim 12 , wherein the sensing line is connected to a dummy channel to which a dummy reference voltage is supplied,

wherein the characteristic value sensing switch is configured to control a connection between the dummy channel and a node to which the dummy reference voltage is supplied, and

wherein the gate sensing switch is configured to control a connection between the dummy channel and the node to which the compensating high-potential gate voltage is supplied.

14. The display device of claim 1 , wherein the timing controller is configured to determine an error in the gate driving circuit based on the compensating high-potential gate voltage and output a gate error signal or control the high-potential gate voltage.

15. A gate driving circuit configured to supply a plurality of scan signals through a plurality of gate lines to a display panel having a plurality of subpixels, the gate driving circuit comprising:

a plurality of gate driving integrated circuits,

wherein at least one of the plurality of gate driving integrated circuits is configured as a feedback gate driving integrated circuit including a feedback circuit and is configured to receive a compensating high-potential gate voltage generated based on a feedback voltage generated by the feedback circuit,

wherein the gate driving integrated circuit includes:

a line selection unit configured to charge an M node based on a previous carry signal in response to an input of a line sensing preparation signal;

a Q node control unit configured to charge a Q node to a level of a first high-potential gate voltage in response to the previous carry signal and discharge the Q node to a level of a third low-potential gate voltage in response to an input of a subsequent carry signal;

a Q node stabilization unit configured to discharge the Q node and a QH node to the level of the third low-potential gate voltage in response to a voltage of a QB node;

an inverter unit configured to change a voltage level of the QB node according to a voltage level of the Q node;

a QB node stabilization unit configured to discharge the QB node to the level of the third low-potential gate voltage in response to the subsequent carry signal, a reset signal, and the charging voltage of the M node;

a carry signal output unit configured to output a current carry signal based on a voltage level of a carry clock signal or the level of the third low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node; and

a scan signal output unit configured to output a plurality of scan signals based on voltage levels of a plurality of scan clock signals or a level of a first low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node.

16. The gate driving circuit of claim 15 , wherein the feedback gate driving integrated circuit includes:

a Q node stabilization unit comprising a first transistor and a second transistor, and a QB node connecting a first gate of the first transistor to a second gate of the second transistor,

wherein the feedback circuit is connected to an output of the QB node.

17. The gate driving circuit of claim 16 , wherein the feedback circuit includes:

at least two feedback transistors having gates connected jointly to the output of the QB node and source nodes connected jointly to a feedback line for transferring the feedback voltage.

18. The gate driving circuit of claim 15 , wherein the compensating high-potential gate voltage corresponds to a second high-potential gate voltage driving the Q node stabilization unit.

19. The gate driving circuit of claim 15 , wherein the feedback circuit includes at least one feedback transistor having a gate node connected to the QB node, a drain node connected to a node for supplying the first low-potential gate voltage, and a source node connected to a feedback line for transferring the feedback voltage.

20. A power management circuit, comprising:

a high-potential gate voltage, configured to:

receive a feedback voltage, and

output a compensating high-potential gate voltage based on the feedback voltage,

wherein the high-potential gate voltage compensation circuit includes:

an amplifier having a non-inverting input terminal to which the feedback voltage is applied;

a reference resistor connected to an inverting input terminal of the amplifier to transfer a reference voltage;

at least one setting resistor connected to the non-inverting input terminal of the amplifier to transfer at least one setting voltage; and

a feedback resistor connected between the inverting input terminal and an output terminal of the amplifier.

21. A display device, comprising:

a display panel having a plurality of subpixels;

a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, and output a feedback voltage;

a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines;

a power management circuit configured to:

supply a plurality of driving voltages to the gate driving circuit and the data driving circuit, and

supply a compensating high-potential gate voltage to the gate driving circuit based on the feedback voltage transferred from the gate driving circuit; and

a timing controller configured to control the gate driving circuit, the data driving circuit, and the power management circuit,

wherein the gate driving circuit includes a plurality of gate driving integrated circuits,

wherein at least one of the plurality of gate driving integrated circuits is configured as a feedback gate driving integrated circuit including a feedback circuit for outputting the feedback voltage, and

wherein the data driving circuit includes:

an analog-to-digital converter configured to sense a voltage of a sensing line and convert the voltage into digital data;

a characteristic value sensing switch configured to control a connection between the sensing line and a node to which a sensing reference voltage is supplied;

a gate sensing switch configured to control a connection between the sensing line and a node to which the compensating high-potential gate voltage is supplied; and

a sampling switch configured to control a connection between the sensing line and the analog-to-digital converter.