Reducing parasitic capacitance in field-effect transistors
View Patent ↗A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.
1. A method, comprising:
receiving a workpiece comprising:
a plurality of semiconductor fins over a substrate, wherein the plurality of semiconductor fins comprises one or more inner semiconductor fins and two outermost semiconductor fins, and
a first dielectric fin disposed adjacent to a first outermost semiconductor fin of the two outermost semiconductor fins, wherein the first dielectric fin has a top surface coplanar with a top surface of the first outermost semiconductor fin and a bottom surface above a bottom surface of the first outermost semiconductor fin;
forming a gate structure over the first dielectric fin and the plurality of semiconductor fins; and
forming a source/drain feature over the first outermost semiconductor fin and adjacent to the gate structure, wherein an air gap is enclosed by the source/drain feature and the first dielectric fin.
2. The method of claim 1 ,
wherein the workpiece further comprises a plurality of isolation features,
wherein two adjacent semiconductor fins of the semiconductor fins are separated by a first isolation feature of the plurality of isolation features, and the first outermost semiconductor fin and the first dielectric fin are separated by a second isolation feature of the plurality of isolation features, and
wherein the first dielectric fin partially extends into the second isolation feature.
3. The method of claim 2 , wherein a composition of the plurality of isolation features is different than a composition of the first dielectric fin.
4. The method of claim 1 , further comprising:
after the forming of the gate structure, conformally depositing a spacer layer over the workpiece; and
etching back the spacer layer to form gate spacers extending along sidewall surfaces of the gate structure and fin spacers extending along bottom portions of sidewall surfaces of the plurality of semiconductor fins and the first dielectric fin.
5. The method of claim 4 , wherein a dielectric constant of the first dielectric fin is less than a dielectric constant of the spacer layer.
6. The method of claim 4 , further comprising:
after the forming of the source/drain feature, selectively removing the gate structure to form a gate trench; and
forming a metal gate stack in the gate trench.
7. The method of claim 6 , wherein the gate trench exposes a portion of the first dielectric fin.
8. The method of claim 1 , wherein the workpiece further comprises a second dielectric fin disposed adjacent to a second outermost semiconductor fin of the two outermost semiconductor fins.
9. The method of claim 1 , wherein each of the plurality of semiconductor fins comprises a vertical stack of alternating channel layers and sacrificial layers, and the method further comprises:
after the forming of the source/drain feature, selectively removing the gate structure and the sacrificial layers; and
forming a gate stack over and wrapping around each of the channel layers.
10. A method, comprising:
providing a substrate having a first region and a second region adjacent to the first region;
forming one or more semiconductor fins over the first region of the substrate;
forming a dielectric fin over the second region of the substrate;
forming a gate structure intersecting the dielectric fin and the one or more semiconductor fins;
selectively recessing source/drain regions of the one or more semiconductor fins without substantially etching the dielectric fin to form source/drain trenches; and
forming source/drain features in the source/drain trenches, wherein an air gap is enclosed by one of the source/drain features and the dielectric fin.
11. The method of claim 10 , further comprising:
after the forming of the one or more semiconductor fins, depositing a first dielectric layer over the one or more semiconductor fins;
planarizing the first dielectric layer until a top surface of the first dielectric layer is coplanar with a top surface of the one or more semiconductor fins; and
after the planarizing of the first dielectric layer, recessing the first dielectric layer to form an isolation feature adjacent to the one or more semiconductor fins.
12. The method of claim 11 , wherein the forming of the dielectric fin comprises:
after the planarizing of the first dielectric layer, forming a dielectric fin trench in the first dielectric layer and over the second region of the substrate;
depositing a second dielectric layer over the substrate to fill the dielectric fin trench; and
planarizing the second dielectric layer until a top surface of the second dielectric layer is coplanar with a top surface of the one or more semiconductor fins to form the dielectric fin.
13. The method of claim 12 , wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer.
14. The method of claim 10 , further comprising:
after the forming of the gate structure, conformally depositing a spacer layer over the substrate; and
etching back the spacer layer to form gate spacers extending along sidewall surfaces of the gate structure and fin spacers extending along lower portions of sidewall surfaces of the one or more semiconductor fins and the dielectric fin.
15. The method of claim 10 , wherein the forming of the one or more semiconductor fins comprises:
forming a vertical stack of alternating channel layers and sacrificial layers over the substrate; and
patterning the vertical stack and a top portion of the substrate to form the one or more semiconductor fins over the first region of the substrate.
16. The method of claim 15 , further comprising:
selectively removing the gate structure;
selectively removing the sacrificial layers; and
forming a gate stack to wrap around each of the channel layers.
17. A semiconductor structure, comprising:
a substrate having a first region and a second region adjacent to the first region;
one or more semiconductor fins over the first region of the substrate;
a dielectric fin over the second region of the substrate, wherein a top surface of the dielectric fin is coplanar with a top surface of the one or more semiconductor fins;
a gate structure intersecting the dielectric fin and the one or more semiconductor fins; and
source/drain features adjacent to the gate structure and coupled to the one or more semiconductor fins, wherein an air gap is enclosed by one of the source/drain features and the dielectric fin, and wherein a bottom surface of the dielectric fin is above a bottom surface of the one or more semiconductor fins.
18. The semiconductor structure of claim 17 , further comprising:
dielectric spacers extending along bottom portions of sidewall surfaces of the one or more semiconductor fins and the dielectric fin.
19. The semiconductor structure of claim 17 , further comprising:
an etch-stop layer over the source/drain features and the dielectric fin, such that the etch-stop layer partially fills the air gap.
20. The semiconductor structure of claim 17 , wherein each of the one or more semiconductor fins comprises a plurality of nanostructures.