Interconnect structure and methods of forming the same
View Patent ↗An interconnect structure, along with methods of forming such, are described. In some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.
1. A method, comprising:
forming a first dielectric layer over one or more devices;
forming a first conductive feature in the first dielectric layer;
forming two dielectric features over the first dielectric layer and the first conductive feature, wherein at least one of the dielectric features has a first width, and wherein each dielectric feature comprises a first low-k dielectric layer, an oxide layer, and a first etch stop layer; and
forming a second conductive feature between the two dielectric features, wherein the second conductive feature has a second width substantially the same as the first width.
2. The method of claim 1 , wherein the oxide layer comprises a semiconductor oxide, and the first etch stop layer comprises a nitride or a metal oxide.
3. The method of claim 2 , wherein the oxide layer is silicon dioxide, and the first low-k dielectric layer comprises SiCOH.
4. The method of claim 1 , wherein the first width and the second width each ranges from about 10 nm to about 15 nm.
5. The method of claim 1 , wherein the second conductive feature is aligned with the first conductive feature.
6. The method of claim 1 , further comprising:
a second etch stop layer disposed over the two dielectric features and the second conductive feature;
a second low-k dielectric layer disposed on the second etch stop layer; and
a third conductive feature disposed in the second low-k dielectric layer.
7. A method, comprising:
forming an oxide layer on a first etch stop layer;
forming a sacrificial layer on the oxide layer;
patterning the sacrificial layer to form a plurality of openings in the sacrificial layer;
forming a first low-k dielectric layer on the patterned sacrificial layer and the oxide layer;
removing portions of first low-k dielectric layer disposed on horizontal surfaces of the patterned sacrificial layer and on horizontal surfaces of the oxide layer to form a plurality of portions of the first low-k dielectric layer;
removing the patterned sacrificial layer; and
forming a conductive material between adjacent portions of the plurality of portions of the first low-k dielectric layer.
8. The method of claim 7 , further comprising forming a first multilayer structure on the sacrificial layer before patterning the sacrificial layer, wherein the first multilayer structure comprises first one or more layers and a first photoresist layer.
9. The method of claim 8 , further comprising removing portions of the first one or more layers of the first multilayer structure before patterning the sacrificial layer.
10. The method of claim 9 , wherein the removing the portions of the first one or more layers of the first multilayer structure and patterning the sacrificial layer are performed in the same etch chamber.
11. The method of claim 7 , wherein the first low-k dielectric layer is a conformal layer formed by atomic layer deposition.
12. The method of claim 11 , wherein the forming the plurality of portions of the first low-k dielectric layer comprises removing portions of the first low-k dielectric layer disposed on horizontal surfaces.
13. The method of claim 12 , further comprising forming a second multilayer structure over the patterned sacrificial layer before removing the patterned sacrificial layer, wherein the second multilayer structure comprises second one or more layers and a second photoresist layer.
14. The method of claim 13 , further comprising removing portions of the second one or more layers of the second multilayer structure before removing the patterned sacrificial layer.
15. The method of claim 14 , wherein the removing the portions of the second one or more layers of the second multilayer structure and removing the patterned sacrificial layer are performed in the same etch chamber.
16. The method of claim 7 , further comprising forming a second low-k dielectric layer over the conductive material and the portions of the first low-k dielectric layer.
17. A method, comprising:
forming a sacrificial layer on an oxide layer;
forming a multilayer structure on the sacrificial layer, wherein the multilayer structure comprises a photoresist layer disposed on one or more layers;
removing portions of the one or more layers by a first plasma etch process, wherein the first plasma etch process comprises using a first frequency;
removing portions of the sacrificial layer to form a patterned sacrificial layer having a plurality of openings by a second plasma etch process, wherein the second plasma etch process comprises using a second frequency substantially less than the first frequency, wherein the first and second plasma etch processes are performed in the same etch chamber;
forming a low-k dielectric layer on the patterned sacrificial layer, wherein the low-k dielectric layer partially fills the plurality of openings; and
filling the plurality of openings with a conductive material.
18. The method of claim 17 , wherein the low-k dielectric layer is a conformal layer formed by atomic layer deposition.
19. The method of claim 17 , further comprising removing portions of the low-k dielectric layer.
20. The method of claim 19 , further comprising removing portions of the oxide layer and portions of an etch stop layer disposed under the oxide layer.