Semiconductor device fabrication methods and structures thereof

1. A method comprising:

providing a first channel layer and a second channel layer over a substrate;

forming a first patterned hard mask covering the first channel layer and exposing the second channel layer;

selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask, wherein the cladding layer includes a p-dipole material or a precursor of a p-dipole material;

after depositing the cladding layer, performing a first thermal drive-in process;

removing the first patterned hard mask;

after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and

forming a high-k dielectric layer on the interfacial dielectric layer.

2. The method of claim 1 , further comprising:

after removing the first patterned hard mask and before forming the interfacial dielectric layer, performing a cleaning process with an oxygen-containing cleaning solution to the first channel layer, the cladding layer, and the second channel layer, resulting in a first dipole layer wrapping around the second channel layer and the interfacial dielectric layer wrapping around the first channel layer and the first dipole layer.

3. The method of claim 2 , wherein the first dipole layer includes germanium oxide, aluminum oxide, gallium oxide, or zinc oxide.

4. The method of claim 2 , wherein the oxygen-containing cleaning solution includes standard clean 1 (SC1) solution or standard clean 2 (SC2) solution.

5. The method of claim 1 , further comprising:

forming a second dipole layer wrapping around the high-k dielectric layer over the second channel layer but not the high-k dielectric layer over the first channel layer;

performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer over the second channel layer;

removing the second dipole layer; and

forming a work function metal layer wrapping around the high-k dielectric layer over both the first and the second channel layers.

6. The method of claim 5 , wherein the forming of the second dipole layer includes:

depositing the second dipole layer wrapping around the high-k dielectric layer over both the first and the second channel layers;

forming a patterned hard mask covering the second dipole layer over the second channel layer and exposing the second dipole layer over the first channel layer;

selectively removing the second dipole layer over the first channel layer to expose the high-k dielectric layer over the first channel layer; and

selectively removing the patterned hard mask to expose the second dipole layer over the second channel layer.

7. The method of claim 5 , wherein the second dipole layer includes lanthanum oxide, yttrium oxide, or titanium oxide.

8. The method of claim 5 , wherein the work function metal layer includes titanium nitride, tantalum nitride, tungsten carbonitride, or titanium silicon nitride.

9. A method comprising:

providing semiconductor channel layers over a substrate;

forming an interfacial dielectric layer wrapping around the semiconductor channel layers;

forming a first dipole layer over the interfacial dielectric layer;

performing a first thermal process, thereby driving first dipole elements from the first dipole layer into the interfacial dielectric layer;

removing remaining portions of the first dipole layer;

forming a high-k dielectric layer wrapping around the interfacial dielectric layer;

forming a second dipole layer wrapping around the high-k dielectric layer;

performing a second thermal process, thereby driving second dipole elements from the second dipole layer into the high-k dielectric layer;

removing remaining portions of the second dipole layer; and

forming a work function metal layer wrapping around the high-k dielectric layer.

10. The method of claim 9 , wherein the work function metal layer fills gaps between adjacent semiconductor channel layers.

11. The method of claim 9 , wherein the work function metal layer is free of aluminum.

12. The method of claim 9 , wherein the work function metal layer includes titanium nitride, tantalum nitride, tungsten carbonitride, or titanium silicon nitride.

13. The method of claim 9 , wherein the first dipole elements include lanthanum oxide, yttrium oxide, or titanium oxide.

14. The method of claim 9 , wherein the second dipole elements include germanium oxide, aluminum oxide, gallium oxide, or zinc oxide.

15. The method of claim 9 , further comprising forming a gate electrode layer over the work function metal layer.

16. A semiconductor structure, comprising:

a substrate;

a semiconductor channel layer over the substrate;

an interfacial dielectric layer over the semiconductor channel layer;

a high-k dielectric layer over the interfacial dielectric layer;

a work function metal layer over the high-k dielectric layer and wrapping around the semiconductor channel layer;

first dipole elements distributed along an interface between the semiconductor channel layer and the interfacial dielectric layer; and

second dipole elements distributed along another interface between the interfacial dielectric layer and the high-k dielectric layer, wherein the first and the second dipole elements have opposite polarities.

17. The semiconductor structure of claim 16 , wherein the first dipole elements include a p-dipole material and the second dipole elements include an n-dipole material.

18. The semiconductor structure of claim 16 , wherein the first dipole elements include an n-dipole material and the second dipole elements include a p-dipole material.

19. The semiconductor structure of claim 16 , wherein the work function metal layer is substantially free of aluminum.

20. The semiconductor structure of claim 16 , wherein the semiconductor channel layer includes crystalline silicon, the first dipole elements include germanium dioxide, and the interfacial dielectric layer includes silicon dioxide.