IP Library › Granted Patent US 11,997,401
Granted Patent B2
US 11,997,401 · App. 17/832,029 · Granted May 28, 2024

Image sensor, image acquisition apparatus, and electronic apparatus with improved performance

Inventors: Jungwoo Kim (Hwaseong-si, KR); Byeongil Min (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H04N25/40H04N25/58H04N25/704H04N25/75
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,997,401
App. No.
17/832,029
Granted
May 28, 2024
Kind
B2
Abstract

Provided is an image sensor using photon counting, the image sensor including a pixel including a plurality of sub-pixels, a plurality of counters which are respectively connected to the plurality of sub-pixels and configured to count and output a plurality of pulse signals generated based on photons incident on each of the plurality of sub-pixels, and an operator configured to perform an operation on an output value output from each of the plurality of counters.

Claims (41)

1. An image sensor using photon counting, the image sensor comprising a pixel:

wherein the pixel comprises:

a plurality of sub-pixels;

a plurality of counters which are respectively connected to the plurality of sub-pixels and configured to count and output a plurality of pulse signals generated based on photons incident on each of the plurality of sub-pixels; and

an operator circuit configured to perform an operation on an output value output from each of the plurality of counters; and

wherein the operator circuit being configured to perform the operation includes being configured to perform addition, subtraction, multiplication, and division.

2. The image sensor of claim 1 , wherein each of the plurality of sub-pixels is a single photon avalanche diode (SPAD).

3. The image sensor of claim 1 , wherein the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel.

4. The image sensor of claim 1 , wherein the operation is any of an addition, a subtraction, a multiplication, and a division.

5. The image sensor of claim 4 , wherein at least one operation from among the addition, the subtraction, the multiplication, and the division is preset.

6. The image sensor of claim 3 , wherein the operator circuit is further configured to output a result value obtained by performing a subtraction operation on a first output value output from a first counter connected to the first sub-pixel and a second output value output from a second counter connected to the second sub-pixel.

7. The image sensor of claim 1 , wherein sizes of the plurality of sub-pixels are different from each other.

8. An image acquisition apparatus comprising a pixel array comprising a plurality of pixels:

wherein each of the plurality of pixels comprises

a plurality of sub-pixels;

a plurality of counters which are respectively connected to the plurality of sub-pixels and are configured to count and output a plurality of pulse signals generated based on photons incident on each of the plurality of sub-pixels; and

an operator circuit configured to perform an operation on an output value output from each of the plurality of counters;

wherein the operator circuit being configured to perform the operation includes being configured to perform addition, subtraction, multiplication, and division; and

wherein the image acquisition apparatus further comprises a processor configured to process an operation value output from an operator circuit of each of the plurality of pixels.

9. The image acquisition apparatus of claim 8 , wherein each of the plurality of sub-pixels is a single photon avalanche diode (SPAD).

10. The image acquisition apparatus of claim 8 , wherein the operation is any of an addition, a subtraction, a multiplication, and a division.

11. The image acquisition apparatus of claim 10 , wherein the processor is further configured to set any operation from among the addition, the subtraction, the multiplication, and the division.

12. The image acquisition apparatus of claim 8 , wherein the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel.

13. The image acquisition apparatus of claim 12 , wherein the operator circuit is further configured to output a result value obtained by performing a subtraction operation on a first output value output from a first counter connected to the first sub-pixel and a second output value output from a second counter connected to the second sub-pixel.

14. The image acquisition apparatus of claim 13 , wherein the processor is further configured to perform a phase difference auto focusing (AF) based on a plurality of result values respectively output from operators of the pixel array.

15. The image acquisition apparatus of claim 8 , wherein the processor is further configured to output a select signal for each of the plurality of sub-pixels.

16. The image acquisition apparatus of claim 8 , wherein a first sub-pixel from among the plurality of sub-pixels is a pixel having a first luminance, and

wherein a second sub-pixel from among the plurality of sub-pixels is a pixel having a second luminance that is higher than the first luminance.

17. The image acquisition apparatus of claim 8 , wherein sizes of the plurality of sub-pixels are different from each other.

18. The image acquisition apparatus of claim 8 , wherein each of the pixel array and a readout circuit corresponds to an M×N array, and,

when the number of the plurality of sub-pixels is K, a resolution of an image obtained from the pixel array is K×M×N.

19. The image acquisition apparatus of claim 8 ,

wherein the processor is provided outside of the each of the plurality of pixels.

20. An electronic apparatus comprising an image acquisition apparatus:

wherein the image acquisition apparatus comprises a pixel array comprising a plurality of pixels;

wherein each of the plurality of pixels comprises:

a plurality of sub-pixels;

a plurality of counters which are respectively connected to the plurality of sub-pixels and are configured to count and output a plurality of pulse signals generated based on photons incident on each of the plurality of sub-pixels; and

an operator circuit configured to perform an operation on an output value output from each of the plurality of counters;

wherein the operator circuit being configured to perform the operation includes being configured to perform addition, subtraction, multiplication, and division; and

wherein the image acquisition apparatus further comprises a processor configured to process an operation value output from an operator circuit of each of the plurality of pixels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2022
From: KIM, JUNGWOO; MIN, BYEONGIL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 060100/0047 →
Priority Claims (1)
KR 10-2021-0146059 · Oct 28, 2021 · national
Continuity (1)
Related Publication 20230134771A1 · May 4, 2023
Cited By (1)
US 12,244,953