Memory device and refresh method thereof
A memory device is provided. The memory device includes: a memory cell array including a plurality of rows; and a refresh control circuit including a plurality of registers each configured to store a row address. The refresh control circuit is configured to: determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability; maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.
1. A memory device comprising:
a memory cell array comprising a plurality of rows; and
a refresh control circuit comprising a plurality of registers each configured to store a row address,
wherein the refresh control circuit is configured to:
determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability;
maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and
determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.
2. The memory device of claim 1 , wherein the refresh control circuit is further configured to:
count a number of hits in each of the plurality of registers; and
determine the replacement probability based on a minimum count value among a plurality of count values of the plurality of registers.
3. The memory device of claim 2 , wherein the refresh control circuit further is configured to determine the replacement probability to be inversely proportional to the minimum count value.
4. The memory device of claim 2 , wherein the refresh control circuit is further configured to identify the replacement probability as a reciprocal of a sum of the minimum count value and a positive value.
5. The memory device of claim 2 , wherein the refresh control circuit is further configured to select, as the replacement probability, a probability corresponding to the minimum count value from among the plurality of count values.
6. The memory device of claim 5 , wherein the refresh control circuit is further configured to:
generate a random sequence based on unique identification information of the memory device;
selectively enable a replacement control signal based on the random sequence and the replacement probability; and
replace the first row address stored in the first register with the incoming row address based on the replacement control signal being enabled.
7. The memory device of claim 6 , wherein the unique identification information comprises a physically unclonable function (PUF).
8. The memory device of claim 2 , wherein the first register is a register having the minimum count value among the plurality of registers.
9. The memory device of claim 2 , wherein the second register is a register having a maximum count value among the plurality of registers.
10. The memory device of claim 1 , wherein the refresh control circuit is further configured to:
selectively enable a replacement control signal based on the replacement probability; and
replace the first row address stored in the first register with the incoming row address based on the replacement control signal being enabled.
11. The memory device of claim 1 , wherein the refresh control circuit is further configured to increase a count value of the first register based on the first row address stored in the first register being replaced with the incoming row address according to the first determination.
12. The memory device of claim 1 , wherein the refresh control circuit is further configured to maintain a count value of the first register based on the first row address stored in the first register being maintained according to the first determination.
13. The memory device of claim 1 , wherein the replacement condition comprises a first condition that the incoming row address is different from the row address stored in each of the plurality of registers.
14. The memory device of claim 13 , wherein the replacement condition further comprises a second condition that the plurality of registers does not comprise an empty register.
15. The memory device of claim 1 , wherein the victim row address is adjacent to the second row address.
16. A memory device comprising:
a memory cell array comprising a plurality of rows; and
a refresh control circuit comprising:
a plurality of registers each configured to store a row address;
a plurality of counters respectively corresponding to the plurality of registers, and each configured to count a number of hits in a corresponding register among the plurality of registers;
a first control circuit configured to selectively enable a replacement control signal based on a replacement probability;
a second control circuit configured to, based on an incoming row address indicating a hit register among the plurality of registers, store the incoming row address to the hit register, and to, based on each of the plurality of registers storing a row address that does not correspond to the incoming row address and the replacement control signal being enabled, replace a first row address stored in a first register among the plurality of registers with the incoming row address; and
a calculator configured to identify a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.
17. The memory device of claim 16 , wherein the first control circuit is further configured to determine the replacement probability based on a minimum count value among count values of the plurality of counters.
18. The memory device of claim 17 , wherein the first control circuit is further configured to determine the replacement probability to be inversely proportional to the minimum count value.
19. The memory device of claim 16 , wherein the second control circuit is further configured to, based on the first row address stored in the first register being replaced with the incoming row address, increase a count value of a first counter corresponding to the first register among the plurality of counters.
20. A refresh method of a memory device including a memory cell array including a plurality of rows and a refresh control circuit including a plurality of registers, the refresh method comprising:
receiving an incoming row address;
determining whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address;
maintaining the first row address stored in the first register or replacing the first row address stored in the first register with the incoming row address based on a result of the determining;
determining a victim row address based on a second row address stored in a second register of the plurality of registers; and
refreshing a victim row indicated by the victim row address.