Memory array word line routing

1. A method comprising:

depositing a ferroelectric (FE) material on a first word line;

depositing an oxide semiconductor (OS) layer on the FE material;

patterning a first trench in the OS layer;

depositing a dielectric material in the first trench and on the FE material;

depositing an inter-metal dielectric (IMD) on the first word line;

patterning the IMD to form a second trench exposing the first word line;

patterning the dielectric material and the FE material to form a third trench;

forming a first contact in the second trench;

forming a second contact in the third trench; and

forming a first conductive line electrically coupling the first contact to the second contact.

2. The method of claim 1 , wherein the third trench is patterned to a depth greater than the second trench.

3. The method of claim 1 , wherein the IMD, the dielectric material, and the FE material are patterned simultaneously to form the second trench and the third trench.

4. The method of claim 1 , wherein the first word line is on an interconnect structure wherein the second contact is electrically coupled to the interconnect structure.

5. The method of claim 1 , wherein the third trench is patterned through the IMD.

6. The method of claim 1 , wherein the first contact and the second contact are formed simultaneously.

7. The method of claim 1 , further comprising forming a patterned photoresist on the IMD, wherein the second trench and the third trench are patterned through the patterned photoresist.

8. A method comprising:

patterning a conductive layer in a multi-layer stack to form a word line and a first trench adjacent the word line;

depositing a ferroelectric (FE) material in the first trench;

depositing an oxide semiconductor (OS) layer in the first trench and on the FE material;

patterning the OS layer to form a second trench exposing the FE material;

forming a dielectric material in the second trench;

patterning the dielectric material and the FE material to form a third trench;

forming a first contact in the third trench; and

forming a first conductive line electrically coupled to the first contact and the word line.

9. The method of claim 8 , further comprising forming the multi-layer stack on a first interconnect structure, wherein the first contact is electrically coupled to the first interconnect structure.

10. The method of claim 8 , further comprising:

forming an inter-metal dielectric on the word line;

patterning the inter-metal dielectric to form a fourth trench exposing the word line; and

forming a second contact in the fourth trench, wherein the second contact electrically couples the word line to the first conductive line.

11. The method of claim 10 , wherein the third trench is patterned through the inter-metal dielectric.

12. The method of claim 8 , further comprising patterning the multi-layer stack to form a first staircase structure adjacent a first end of the word line and a second staircase structure adjacent a second end of the word line, wherein the first staircase structure and the second staircase structure are asymmetric in a cross-sectional view.

13. The method of claim 8 , further comprising forming an inter-metal dielectric on the word line, wherein the third trench is patterned through the inter-metal dielectric.

14. The method of claim 13 , further comprising planarizing the first contact, the inter-metal dielectric, and the multi-layer stack.

15. A method comprising:

forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating conductive layers and dielectric layers;

patterning a first trench extending through the multi-layer stack;

depositing a ferroelectric (FE) material along sidewalls and a bottom surface of the first trench;

depositing an oxide semiconductor (OS) layer over the FE material;

depositing a dielectric material over the FE material;

forming an inter-metal dielectric (IMD) over the multi-layer stack;

forming a first conductive contact extending through the IMD to a first conductive layer of the multi-layer stack, wherein the first conductive contact is electrically coupled to the first conductive layer;

forming a second conductive contact extending through the dielectric material and the FE material; and

forming a conductive line electrically coupling the second conductive contact with the first conductive contact.

16. The method of claim 15 , wherein forming the first conductive contact comprises forming a second trench extending through the IMD, wherein the second trench exposes a top surface of the first conductive layer, wherein forming the second conductive contact comprises forming a third trench extending through the dielectric material and the FE material, and wherein the second trench and the third trench are formed simultaneously.

17. The method of claim 15 , further comprising patterning the multi-layer stack such that the conductive layers and the dielectric layers have a staircase shape in a cross-sectional view.

18. The method of claim 17 , further comprising patterning the dielectric material to have the staircase shape in the cross-sectional view, wherein the IMD is formed over the multi-layer stack and the dielectric material after patterning the dielectric material and the multi-layer stack to have the staircase shape.

19. The method of claim 15 , wherein the dielectric material is formed extending through the IMD.

20. The method of claim 15 , wherein the first conductive contact and the second conductive contact are formed by separate processes.