Semiconductor device comprising memory cell array and arithmetic circuit
A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.
1. A semiconductor device comprising:
a memory cell array;
a sense amplifier circuit; and
an arithmetic circuit,
wherein the memory cell array comprises m×n memory cells and at least n wirings,
wherein m and n are each an integer of 2 or more,
wherein the m×n memory cells are arranged in a matrix,
wherein the sense amplifier circuit comprises at least n first circuits,
wherein each of the n wirings is electrically connected to m of the memory cells,
wherein the n wirings are electrically connected to the n first circuits,
wherein the arithmetic circuit comprises s second circuits,
wherein s is an integer of 1 or more and n or less,
wherein the second circuit is electrically connected to t of the first circuits,
wherein t is an integer of 1 or more and s×t is an integer of n or less,
wherein the second circuit performs an arithmetic operation using a signal of a weight coefficient output from the first circuit, and
wherein the s second circuits perform parallel arithmetic operations.
2. A semiconductor device comprising:
a memory cell array;
a sense amplifier circuit; and
an arithmetic circuit,
wherein a first signal is input to the semiconductor device,
wherein the memory cell array comprises m×n memory cells and at least n wirings,
wherein m and n are each an integer of 2 or more,
wherein the m×n memory cells are arranged in a matrix,
wherein the sense amplifier circuit comprises at least n first circuits,
wherein each of the n wirings is electrically connected to m of the memory cells,
wherein the n wirings are electrically connected to the n first circuits,
wherein the arithmetic circuit comprises s second circuits,
wherein s is an integer of 1 or more and n or less,
wherein the second circuit is electrically connected to t of the first circuits,
wherein t is an integer of 1 or more and s×t is an integer of n or less,
wherein a second signal of a weight coefficient is input from the first circuit to each of the second circuits,
wherein the second circuit performs an arithmetic operation using the first signal and the second signal, and
wherein the s second circuits perform parallel arithmetic operations.
3. The semiconductor device according to claim 1 ,
wherein the memory cell comprises a transistor, and
wherein the transistor comprises a metal oxide in a channel formation region.
4. The semiconductor device according to claim 1 ,
wherein the first circuit and the second circuit each comprise a transistor formed on a semiconductor substrate,
wherein the memory cell comprises a transistor formed in an element layer, and the element layer is stacked over the semiconductor substrate.
5. The semiconductor device according to claim 4 , wherein the transistor of the memory cell comprises a metal oxide in a channel formation region.
6. A semiconductor device comprising:
a memory cell array;
a sense amplifier circuit,
a multiplexer circuit, and
an arithmetic circuit,
wherein the memory cell array comprises m×n memory cells and at least n wirings,
wherein m and n are each an integer of 2 or more,
wherein the m×n memory cells are arranged in a matrix,
wherein the sense amplifier circuit comprises at least n first circuits,
wherein each of the n wirings is electrically connected to m of the memory cells,
wherein the n wirings are electrically connected to the n first circuits,
wherein the multiplexer circuit has a function of selecting s wirings from the n wirings and electrically connecting the first circuits electrically connected to the s wirings and the arithmetic circuit,
wherein s is an integer of 1 or more and n or less,
wherein the arithmetic circuit comprises t second circuits,
wherein t is an integer of 1 or more and s or less,
wherein the second circuit is electrically connected to u of the first circuits,
wherein u is an integer of 1 or more and t×u is an integer of s or less,
wherein the second circuit performs an arithmetic operation using a signal of a weight coefficient output from the first circuit, and
wherein the s second circuits perform parallel arithmetic operations.
7. The semiconductor device according to claim 6 ,
wherein the memory cell comprises a transistor, and the transistor comprises a metal oxide in a channel formation region.
8. The semiconductor device according to claim 6 ,
wherein the first circuit, the multiplexer circuit, and the second circuit each comprise a transistor formed on a semiconductor substrate,
wherein the memory cell comprises a transistor formed in an element layer, and
wherein the element layer is stacked over the semiconductor substrate.
9. The semiconductor device according to claim 8 , wherein the transistor of the memory cell comprises a metal oxide in a channel formation region.
10. A semiconductor device according to claim 1 , wherein the second circuit performs a product-sum operation.
11. A semiconductor device according to any one of claim 2 , wherein the second circuit performs a product-sum operation.
12. A semiconductor device according to any one of claim 6 , wherein the second circuit performs a product-sum operation.
13. The semiconductor device according to claim 2 ,
wherein the memory cell comprises a transistor, and
wherein the transistor comprises a metal oxide in a channel formation region.
14. The semiconductor device according to claim 2 ,
wherein the first circuit and the second circuit each comprise a transistor formed on a semiconductor substrate,
wherein the memory cell comprises a transistor formed in an element layer, and the element layer is stacked over the semiconductor substrate.
15. The semiconductor device according to claim 14 , wherein the transistor of the memory cell comprises a metal oxide in a channel formation region.