Method of manufacturing a III-N enhancement mode HEMT device

1. A method comprising:

providing a semiconductor structure comprising:

a substrate;

a layer stack, wherein each layer of the layer stack comprises a Group III-nitride material; and

a p-type doped GaN layer on the layer stack;

providing, on the p-type doped GaN layer, a metal bi-layer, thereby forming a Schottky junction with the p-type doped GaN layer, the metal bi-layer comprising a first metal layer in contact with the p-type doped GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer; and

performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the p-type doped GaN layer parallel to the first cross section, wherein performing the patterning process comprises:

performing a first dry etching process using a first dry etch chemistry, thereby partially patterning the metal bi-laver, wherein a first etch rate of the first metal layer is less than a second etch rate of the second metal layer;

performing a second dry etching process using a second dry etch chemistry different from the first dry etch chemistry, thereby patterning the p-type doped GaN layer; and

performing a wet etching process upon the metal bi-layer.

2. The method according to claim 1 , wherein the first cross section is substantially the same at every position between the p-type doped GaN layer and a surface of the metal bi-layer opposite the p-type doped GaN layer.

3. The method according to claim 1 , wherein a thickness of the second metal layer is within a range of 50 nm to 500 nm.

4. The method according to claim 1 , wherein the first metal layer comprises TiN and the second metal layer comprises W.

5. The method according to claim 1 , wherein the wet etching process is configured such that the first metal layer has a greater etch rate than the second metal layer so that the first periphery is aligned to the second periphery.

6. The method according to claim 1 , wherein the wet etching process comprises subjecting, at a temperature in a range of 60° C.-95° C., the semiconductor structure to a chemistry comprising H 2 SO 4 and H 2 O 2 .

7. The method according to claim 1 , wherein the first dry etch chemistry comprises CHF 3 and SF 6 .

8. The method according to claim 1 , wherein performing the second dry etching process comprises:

performing a third dry etching process using a third dry etch chemistry, thereby non-selectively etching the p-type doped GaN layer with respect to a layer beneath the p-type doped GaN layer, and

performing a fourth dry etching process using a fourth dry etch chemistry different from the third dry etch chemistry, thereby selectively etching the p-type doped GaN layer with respect to the layer beneath the p-type doped GaN layer.

9. The method according to claim 1 , wherein the layer stack comprises:

a buffer layer overlying the substrate;

a channel layer on the buffer layer; and

a barrier layer on the channel layer, wherein a surface of the layer stack is comprised in the barrier layer.

10. The method according to claim 1 , wherein a thickness of the second metal layer is within a range of 80 nm to 120 nm.

11. The method according to claim 1 , wherein the first metal layer comprises a third metal layer comprising TiN and a fourth metal layer comprising TaN.

12. The method according to claim 11 , wherein the second metal layer comprises W.

13. The semiconductor structure method according to claim 11 , wherein the fourth metal layer contacts the p-type doped GaN layer.

14. The method according to claim 11 , wherein the fourth metal layer has a thickness within a range of 1 nm to 2 nm.