IP Library › Granted Patent US 12,002,737
Granted Patent B2
US 12,002,737 · App. 16/568,990 · Granted Jun 4, 2024

Electronic package and method of fabricating the same

Inventors: Pin-Jing Su (Taichung, TW); Cheng-Kai Chang (Taichung, TW)
Assignee: Siliconware Precision Industries Co., Ltd.
H01L23/481H01L21/566H01L23/3157H01L23/49811H01L23/49827H01L24/33H01L24/83
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Quick Facts
Patent No.
US 12,002,737
App. No.
16/568,990
Granted
Jun 4, 2024
Kind
B2
Abstract

An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.

Claims (11)

1. An electronic package, comprising:

an encapsulating layer;

at least one interposer board embedded into the encapsulating layer and having a plurality of through-silicon vias;

a plurality of conductive pillars disposed in the encapsulating layer and free from being formed in the at least one interposer board and any interposer board, wherein the plurality of conductive pillars are in direct contact with the encapsulating layer and are free from being in direct contact with the at least one interposer board and the plurality of through-silicon vias, wherein a surface of the encapsulating layer, a surface of the at least one interposer board, end surfaces of the plurality of through-silicon vias and end surfaces of the plurality of conductive pillars are horizontally coplanar; and

at least one semiconductor chip as an electronic component disposed on the encapsulating layer and electrically connected to the plurality of conductive pillars and the plurality of through-silicon vias by a plurality of conductive bumps, wherein the plurality of conductive bumps are in direct contact with the electronic component, the plurality of conductive pillars, and the plurality of through-silicon vias, and the electronic component is free from being embedded in the encapsulating layer.

2. The electronic package of claim 1 , wherein the plurality of through-silicon vias or an end surface of the plurality of conductive pillars are exposed from a surface of the encapsulating layer.

3. The electronic package of claim 1 , wherein an active component, a passive component or a combination thereof is disposed on the encapsulating layer.

4. The electronic package of claim 1 , further comprising a wiring structure electrically connecting the electronic component to the conductive pillars and the through-silicon vias.

5. The electronic package of claim 1 , further comprising a wiring structure disposed on the encapsulating layer and electrically connected to the plurality of conductive pillars and the plurality of through-silicon vias.

6. The electronic package of claim 5 , further comprising a plurality of conductive elements disposed on the wiring structure and electrically connected via the wiring structure to the plurality of conductive pillars and the plurality of through-silicon vias.

7. The electronic package of claim 1 , further comprising a plurality of conductive elements disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE CITY PREVIOUSLY RECORDED AT REEL: 50360 FRAME: 127. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2024
From: SU, PIN-JING; CHANG, CHENG-KAI
To: SILICONWARE PRECISION INDUSTRIES CO., LTD
Reel/Frame 066970/0755 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2019
From: SU, PIN-JING; CHANG, CHENG-KAI
To: SILICONWARE PRECISION INDUSTRIES CO., LTD
Reel/Frame 050360/0127 →
Priority Claims (1)
TW 108116577 · May 14, 2019 · national
Continuity (1)
Related Publication 20200365489A1 · Nov 19, 2020