Interconnect structure

1. An interconnect structure, comprising:

a first metal line and a second metal line surrounded by a first dielectric layer;

wherein the second metal line comprises a glue layer, a metal bulk layer over the glue layer and a metal capping layer over the metal bulk layer;

a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line;

a second dielectric layer over the dielectric block, the first metal line and the second metal line, wherein a bottom surface of the second dielectric layer is lower than a top surface of the dielectric block;

a first via surrounded by the second dielectric layer and electrically connected to the first metal line;

an encapsulating layer interposing between the first metal line and the first dielectric layer, wherein a top surface of the second metal line is substantially level to a top surface of the encapsulating layer; and

an etching stop layer along and in contact with the top surface of the second metal line and the top surface of the dielectric block, wherein a bottom surface of the etching stop layer is level to the top surface of the encapsulating layer and a top surface of the metal capping layer.

2. The interconnect structure as claimed in claim 1 , wherein the glue layer, the metal bulk layer and the metal capping layer are in contact with the encapsulating layer.

3. The interconnect structure as claimed in claim 1 , further comprising:

a transistor over a substrate;

a contact plug over a source/drain feature of the transistor; and

a second via over the contact plug, wherein the first metal line is over and in contact with the second via.

4. The interconnect structure as claimed in claim 1 , wherein a portion of the second dielectric layer extends between the first via and the dielectric block.

5. The interconnect structure as claimed in claim 1 , wherein a sidewall and the top surface of the dielectric block are in contact with the first via.

6. The interconnect structure as claimed in claim 1 , wherein a width of the first via is greater than a width of the first metal line.

7. The interconnect structure as claimed in claim 1 , further comprising:

a catalyst layer between the dielectric block and the portion of the first dielectric layer.

8. An interconnect structure, comprising:

a first metal line in a first dielectric layer;

a dielectric block over the first dielectric layer;

an etching stop layer over the dielectric block and the first metal line, wherein the etching stop layer includes a first horizontal portion along a top surface of the first metal line, a first vertical portion along a sidewall of the dielectric block, and a second horizontal portion along a top surface of the dielectric block, and a bottom surface of the first horizontal portion of the etching stop layer is lower than a bottom surface of the dielectric block;

a second dielectric layer covering the first horizontal portion and the second horizontal portion of the etching stop layer; and

a catalyst layer between the dielectric block and the first dielectric layer, wherein the bottom surface of the first horizontal portion of the etching stop layer is level to a bottom surface of the catalyst layer.

9. The interconnect structure as claimed in claim 8 , wherein a top surface of the second horizontal portion is higher than a top surface of the first horizontal portion.

10. The interconnect structure as claimed in claim 8 , further comprising:

a second metal line in the first dielectric layer; and

a via in the second dielectric layer and on the second metal line.

11. The interconnect structure as claimed in claim 10 , wherein a bottom surface of the via is lower than a top surface of the first metal line.

12. The interconnect structure as claimed in claim 10 , wherein the etching stop layer includes a third horizontal portion along a top surface of the second metal line and in contact with the via.

13. The interconnect structure as claimed in claim 10 , wherein a dielectric constant of the etching stop layer is greater than a dielectric constant of the dielectric block.

14. An interconnect structure, comprising:

a first dielectric layer over a substrate;

a first metal line and a second metal line through the first dielectric layer;

a dielectric block over the first dielectric layer;

an etching stop layer along an upper surface and a sidewall of the dielectric block and an upper surface of the second metal line;

a second dielectric layer over the etching stop layer;

a via extending through the second dielectric layer, the etching stop layer, and the dielectric block to the first metal line; and

a blocking layer between the second metal line and the etching stop layer, wherein the blocking layer includes amphiphilic organic molecules.

15. The interconnect structure as claimed in claim 14 , further comprising:

a catalyst layer between the dielectric block and the first dielectric layer; and

an encapsulating layer between first metal line and the first dielectric layer.

16. The interconnect structure as claimed in claim 14 , wherein the via partially covers the dielectric block.

17. The interconnect structure as claimed in claim 1 , wherein the encapsulating layer further interposes between the second metal line and the first dielectric layer, and a top surface of the first metal line is lower than the top surface of the encapsulating layer.

18. The interconnect structure as claimed in claim 14 , wherein the amphiphilic organic molecules include organic sulfur compound, organic phosphor compound, or organic silicon compound.

19. The interconnect structure as claimed in claim 1 , wherein the encapsulating layer is in direct contact with a sidewall of the first via and a sidewall of the first metal line.

20. The interconnect structure as claimed in claim 8 , further comprising:

an encapsulating layer between the first metal line and the first dielectric layer, wherein a sidewall of the catalyst layer is aligned with a sidewall of the encapsulating layer.