IP Library › Granted Patent US 12,002,831
Granted Patent B2
US 12,002,831 · App. 17/266,838 · Granted Jun 4, 2024

Semiconductor device

Inventors: Hajime Yamagishi (Kanagawa, JP); Eiji Sato (Kanagawa, JP); Akira Yamazaki (Kanagawa, JP); Takayuki Sekihara (Kanagawa, JP); Makoto Hayafuchi (Kanagawa, JP); Syunsuke Ishizaki (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/14634H01L24/05H01L24/08H01L27/14636H01L2224/05553H01L2224/08146
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Quick Facts
Patent No.
US 12,002,831
App. No.
17/266,838
Granted
Jun 4, 2024
Kind
B2
Abstract

Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.

Claims (29)

1. A semiconductor device, comprising:

a first semiconductor substrate including a first multilayer wiring layer; and

a second semiconductor substrate including a second multilayer wiring layer, wherein the first semiconductor substrate and the second semiconductor substrate are joined together with the first multilayer wiring layer and the second multilayer wiring layer directly connected to each other to form a plurality of conductors in a proximity of a joining plane of the of the first and second semiconductor substrates, wherein connection holes are formed in either or both of the first multilayer wiring layer and the second multilayer wiring layer, wherein rivets are fitted to the connection holes, and wherein the plurality of conductors are electrified in a direction of the joining plane.

2. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane have a plane long side equal to or greater than twice a width of a connection hole connection face.

3. The semiconductor device according to claim 1 , wherein

only one of the first multilayer wiring layer and the second multilayer wiring layer has the connection holes.

4. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane on a side of the first semiconductor substrate are not electrically connected to an opposing conductor on a side of the second semiconductor substrate.

5. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are different in shape from an opposing conductor.

6. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are arranged in a displaced relation to an opposing conductor by a predetermined direction in a direction of the joining plane.

7. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane have a shape having a plane aspect ratio higher than one.

8. The semiconductor device according to claim 7 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are joined to an opposed conductor on the joining plane so as to cross with each other in a longitudinal direction on the joining plane.

9. The semiconductor device according to claim 7 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are joined to an opposed conductor on the joining plane so as to extend in parallel in a longitudinal direction on the joining plane.

10. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane have a rectangular shape or an elliptical shape having a plane aspect ratio higher than one.

11. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane has a polygonal shape configured from a combination of rectangles having a plane aspect ratio higher than one.

12. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are provided in a region that surrounds an inner side circumference of an input/output pad.

13. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are provided in a rectangular region on an inner side of an input/output pad.

14. The semiconductor device according to claim 1 , wherein

at least some of the plurality of conductors formed in the proximity of the joining plane are provided in parallel to a power supply wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2024
From: YAMAGISHI, HAJIME; SATO, EIJI; YAMAZAKI, AKIRA; SEKIHARA, TAKAYUKI; HAYAFUCHI, MAKOTO; ISHIZAKI, SYUNSUKE
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 067258/0338 →
Priority Claims (1)
JP 2018-162382 · Aug 31, 2018 · national
Continuity (1)
Related Publication 20210351219A1 · Nov 11, 2021