Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer;
forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer;
forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer;
forming a first dielectric layer over the sacrificial cladding layer;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer;
recessing the second dielectric layer;
forming a third dielectric layer made of a different material than the second dielectric layer over the recessed second dielectric layer;
partially removing the third dielectric layer to form a trench; and
forming a fourth dielectric layer by filling the trench with a dielectric material different from the third dielectric layer, thereby forming a wall fin structure.
2. The method of claim 1 , wherein the first dielectric layer includes at least one of SiOC, SiOCN or SiCN.
3. The method of claim 1 , wherein the second dielectric layer includes at least one of silicon nitride, silicon oxide or SiON.
4. The method of claim 1 , wherein the third dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide.
5. The method of claim 1 , wherein the fourth dielectric layer includes SiCN.
6. The method of claim 1 , wherein the trench is formed by plasma etching using a source gas including C 4 F 6 and CHF 3 .
7. The method of claim 1 , wherein the fourth dielectric layer is formed by:
forming a blanket layer of the dielectric material for the fourth dielectric layer; and
performing an etching back operation using plasma etching.
8. The method of claim 7 , wherein a source gas of the plasma etching includes CH 3 F.
9. The method of claim 1 , wherein the sacrificial cladding layer is amorphous or polycrystalline Si or SiGe.
10. A method of manufacturing a semiconductor device, comprising:
forming a fin structure;
forming an isolation insulating layer so that an upper portion of the fin structure is exposed from the isolation insulating layer;
forming a sacrificial layer over at least sidewalls of the exposed upper portion of the fin structure;
forming a first dielectric layer over the sacrificial layer;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer;
recessing the second dielectric layer;
forming a third dielectric layer made of a different material than the second dielectric layer over the recessed second dielectric layer;
partially removing the third dielectric layer to form a trench; and
forming a fourth dielectric layer by filling the trench with a dielectric material different from the third dielectric layer, thereby forming a wall fin structure.
11. The method of claim 10 , further comprising:
recessing a source/drain portion of the fin structure to form a recessed fin structure;
forming a source/drain epitaxial layer over the recessed fin structure;
forming a fifth dielectric layer over the source/drain epitaxial layer;
removing the fourth dielectric layer to form a space;
forming a contact opening in the fifth dielectric layer; and
forming a source/drain contact by filling the contact opening with one or more conductive materials.
12. The method of claim 11 , further comprising, after the fourth dielectric layer is removed, treating the space with plasma so that the third dielectric layer has a V-shape cross section.
13. The method of claim 12 , wherein a source gas of the plasma includes HBr.
14. The method of claim 12 , wherein a part of the source/drain contact is formed over the third dielectric layer having a V-shape cross section.
15. The method of claim 11 , further comprising:
removing the sacrificial layer to expose a channel region of the fin structure;
forming a gate dielectric layer over the channel region; and
forming a gate electrode over the gate dielectric layer.
16. The method of claim 11 , wherein:
the fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and
the method further comprises:
removing the sacrificial layer to expose a channel region of the fin structure;
removing the first semiconductor layers thereby releasing semiconductor wires or sheets formed of the second semiconductor layers;
forming a gate dielectric layer around the semiconductor wires or sheets; and
forming a gate electrode over the gate dielectric layer.
17. The method of claim 10 , wherein the third dielectric layer includes hafnium oxide and the fourth dielectric layer includes SiCN.
18. A method of manufacturing a semiconductor device, comprising:
forming fin structures each including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer;
forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer;
forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer;
forming a first dielectric layer over the sacrificial cladding layer, the first dielectric layer not fully filling a space between the fin structures;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer to fully fill the space between the fin structures;
recessing the second dielectric layer;
forming a third dielectric layer made of a different material than the second dielectric layer over the recessed second dielectric layer;
partially removing the third dielectric layer to form a trench;
forming a fourth dielectric layer by filling the trench with a dielectric material different from the third dielectric layer, thereby forming a wall fin structure;
removing the hard mask layer;
forming a sacrificial gate structure;
forming sidewall spacers on sidewalls of the sacrificial gate structure and sidewalls of a part of the wall fin structure;
forming a source/drain structure adjacent opposing sides of the sidewall spacers;
forming a fifth dielectric layer;
removing the sacrificial gate structure;
removing the sacrificial cladding layer;
removing the first semiconductor layers; and
forming a metal gate structure around the second semiconductor layers.
19. The method of claim 18 , wherein the third dielectric layer includes hafnium oxide and the fourth dielectric layer includes SiCN.
20. The method of claim 19 , further comprising:
removing the fourth dielectric layer to form a space;
forming a contact opening in the fifth dielectric layer; and
forming a source/drain contact by filling the contact opening with one or more conductive materials.