LDMOS having multiple field plates and associated manufacturing method
View Patent ↗An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.
1. A lateral double diffused metal oxide semiconductor field effect transistor (LDMOS), comprising:
a semiconductor substrate having an upper surface;
a source and a drain, formed in the semiconductor substrate;
an interlayer dielectric layer, covering the upper surface of the semiconductor substrate, wherein the interlayer dielectric layer has an upper surface;
a gate conducting layer, disposed in the interlayer dielectric layer between the source and the drain, the gate conducting layer comprises a plate portion and a channel portion, wherein the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate;
a field plate barrier layer, disposed in the interlayer dielectric layer between the plate portion and the drain;
a first field plate, disposed in the interlayer dielectric layer and extending from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer, wherein the first field plate has a lower surface in contact with the field plate barrier layer; and
a second field plate, disposed in the interlayer dielectric layer and extending from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer, wherein the second field plate has a lower surface in contact with the field plate barrier layer;
wherein the height of the lower surface of the first field plate to the upper surface of the semiconductor substrate is greater than the height of the lower surface of the second field plate to the upper surface of the semiconductor substrate, and the height of the lower surface of the second field plate to the upper surface of the semiconductor substrate is greater than the height of the plate portion to the upper surface of the semiconductor substrate.
2. The LDMOS of claim 1 , wherein the field plate barrier layer comprises nitride.