Control for a multi-level inverter
A control circuit for an inverter. The control circuit includes a first pulse width modulation (PWM) module configured to produce first and second complementary PWM signals, and a second PWM module configured to produce a third and fourth complementary PWM signals. PWM switching logic is coupled to the first and second PWM modules and is adapted to be coupled to a switch network. The switch network includes first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal. The PWM switching logic is configured to produce control signals for each of the first, second, third, and fourth switches in response to the first and second complementary PWM signals and to the third and fourth complementary PWM signals.
1. A circuit, comprising:
a first pulse width modulation (PWM) module configured to produce a first pair of complementary PWM signals including a first signal and a second signal;
a second PWM module configured to produce a second pair of complementary PWM signals including a third signal and a fourth signal;
a logic circuit coupled to the first and second PWM modules and configured to produce a fifth signal and a sixth signal, wherein a transition of the fifth signal is delayed with respect to a transition of the first signal, and a transition of the sixth signal is delayed with respect to a transition of the second signal, based on the third signal; and
PWM switching logic coupled to the logic circuit and a switch network, wherein the switch network includes first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal, and wherein the PWM switching logic is configured to produce respective control signals for the first, second, third, and fourth switches based on the third, fourth, fifth, and sixth signals.
2. The circuit of claim 1 , wherein the switch network further includes fifth and sixth switches coupled in series, the series combination of the fifth and sixth switches being in parallel across the second and third switches, and wherein the PWM switching logic is further configured to produce respective control signals for the fifth and sixth switches based on the third, fourth, fifth, and sixth signals.
3. The circuit of claim 2 , wherein the switch network is an active neutral point clamped (ANPC) inverter.
4. The circuit of claim 2 , wherein the PWM switching logic includes:
a first logic gate configured to produce the control signal for the first switch, the first logic gate having first and second inputs, the first input of the first logic gate coupled to the third signal, and the second input of the first logic gate coupled to the fifth signal;
a second logic gate configured to produce the control signal for the fourth switch, the second logic gate having first and second inputs, the first input of the second logic gate coupled to the third signal, and the second input of the second logic gate coupled to the sixth signal;
a third logic gate configured to produce the control signal for the second switch, the third logic gate having an input coupled to the fifth signal; and
a fourth logic gate configured to produce the control signal for the third switch, the fourth logic gate having an input coupled to the sixth signal.
5. The circuit of claim 4 , wherein the first and second logic gates are AND gates, and the third and fourth logic gates are OR gates.
6. The circuit of claim 4 , wherein the PWM switching logic further includes:
a fifth logic gate having first and second inputs and an output, the first input of the fifth logic gate coupled to the fourth signal, and the second input of the fifth logic gate coupled to the fifth signal;
a sixth logic gate configured to produce the control signal for the fifth switch, the sixth logic gate having first and second inputs, the first input of the sixth logic gate coupled to the control signal produced by the second logic gate, and the second input of the sixth logic gate coupled to the output of the fifth logic gate;
a seventh logic gate having first and second inputs and an output, the first input of the seventh logic gate coupled to fourth signal, and the second input of the seventh logic gate coupled to the sixth signal; and
an eighth logic gate configured to produce the control signal for the sixth switch, the eighth logic gate having first and second inputs, the first input of the eighth logic gate coupled to the output of the seventh logic gate, and the second input of the eighth logic gate coupled to the control signal produced by the first logic gate.
7. The circuit of claim 6 , in which the first, second, fifth, and seventh logic gates are AND gates, and the third, fourth, sixth, and eighth logic gates are OR gates.
8. The circuit of claim 1 , wherein the logic circuit is configured to:
determine whether the first signal is in a specific state; and
initiate a delay of the transition of the fifth signal with respect to the transition of the first signal based on a determination that the first signal is in the specific state.
9. The circuit of claim 8 , wherein the logic circuit includes a timer configured to implement the delay of the transition of the fifth signal with respect to the transition of the first signal.
10. The circuit of claim 1 , wherein:
the first and second signals have a first frequency; and
the third and fourth signals have a second frequency that is greater than the first frequency.
11. A system comprising:
a switch network including first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal;
a first pulse width modulation (PWM) module configured to produce first and second complementary PWM signals;
a second PWM module configured to produce a third and fourth complementary PWM signals;
PWM switching logic coupled to the first and second PWM modules and the switch network, the PWM switching logic configured to produce respective control signals for the first, second, third, and fourth switches in response to the first and second complementary PWM signals and the third and fourth complementary PWM signals; and
an extended Ton protection circuit coupled between the first PWM module and the PWM switching logic, the extended Ton protection circuit having an input configured to receive the third complementary PWM signal, and the extended Ton protection circuit configured to delay turning off the second switch after the first switch is turned off, and delay turning off the third switch after the fourth switch is turned off.
12. The circuit system of claim 11 , wherein the extended Ton protection circuit includes a timer to implement a delay in turning off the second and third switches.
13. The circuit system of claim 11 , wherein the switch network is an active neutral point clamped (ANPC) inverter.
14. The circuit system of claim 11 , wherein the switch network further includes fifth and sixth switches coupled in series, the series combination of the fifth and sixth switches being in parallel across the second and third switches, and the PWM switching logic configured to produce respective control signals for the fifth and sixth switches in response to the first and second complementary PWM signals and the third and fourth complementary PWM signals.
15. The circuit system of claim 14 , wherein the PWM switching logic includes:
a first logic gate having first and second inputs, the first input of the first logic gate coupled to the third complementary PWM signal, and the second input of the first logic gate coupled to a signal produced based on the first complementary PWM signal;
a second logic gate having first and second inputs, the first input of the second logic gate coupled to the fourth complementary PWM signal, and the second input of the second logic gate coupled to the signal produced based on the first complementary PWM signal; and
a third logic gate having first and second inputs, the second input of the third logic gate coupled to an output of the second logic gate, and the third logic gate having an output configured to produce the control signal for the fifth switch.
16. The circuit system of claim 15 , wherein the first and second logic gates are AND gates, and the third logic gate is an OR gate.
17. The circuit system of claim 15 , wherein the PWM switching logic further includes:
a fourth logic gate having first and second inputs, the first input of the fourth logic gate coupled to a signal produced based on the second complementary PWM signal, the second input of the fourth logic gate coupled to the third complementary PWM signal, and the fourth logic gate having an output coupled to the first input of the third logic gate.
18. The circuit system of claim 17 , wherein the first, second, and fourth logic gates are AND gates, and the third logic gate is an OR gate.
19. A control circuit for an inverter, comprising:
a first pulse width modulation (PWM) module configured to produce first and second complementary PWM signals;
a second PWM module configured to produce third and fourth complementary PWM signals;
PWM switching logic coupled to the first and second PWM modules and a switch network, the switch network including first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal, and the PWM switching logic configured to produce respective control signals for ach of the first, second, third, and fourth switches in response to the first and second complementary PWM signals and the third and fourth complementary PWM signals; and
an extended Ton protection circuit coupled between the first PWM module and the PWM switching logic, the extended Ton protection circuit having an input configured to receive the third complementary PWM signal, and the extended Ton protection circuit configured to delay turning off the second switch after the first switch is turned off, and delay turning off the third switch after the fourth switch is turned off.
20. The control circuit of claim 19 , wherein the switch network includes fifth and sixth switches, and the PWM switching logic is configured to generate respective control signals for the fifth and sixth switches in response to the first and second complementary PWM signals and the third and fourth complementary PWM signals.