Secure executable code update for a securely-bootable processing chip

1. A method for performing an executable code update, comprising:

receiving, at a processing chip and via a secure network connection, the executable code update to executable code stored in a boot flash chip coupled to the processing chip;

writing, via immutable hardware, the executable code update to a portion of external memory coupled to the processing chip that is only accessible to the immutable hardware of the processing chip;

copying, via the immutable hardware, the executable code update from the portion of the external memory to the boot flash chip; and

establishing the secure network connection between the processing chip and an external entity possessing a public portion of a key with which the executable code update is encrypted, wherein a private portion of the key is unique to the processing chip and is stored solely within the processing chip, wherein the key is generated using a physically unclonable function in autonomous hardware in the processing chip.

2. The method of claim 1 , wherein the private portion of the key is accessible solely by the immutable hardware.

3. The method of claim 1 , wherein the method further comprises:

securely booting one or more central processing units (CPUs) of the processing chip by the immutable hardware performing operations comprising:

reading the executable code update from the boot flash chip;

decrypting the read executable code update using the private portion of the key; and

satisfying an initial instruction fetch of one of the CPUs with a portion of the decrypted executable code update.

4. The method of claim 1 , wherein the method further comprises excluding access by one or more central processing units (CPUs) of the processing chip to the portion of the external memory via an address map; and

wherein the one or more CPUs are configured to be securely booted by the immutable hardware to execute code read from the boot flash chip.

5. The method of claim 4 , wherein the portion of the external memory is a first portion of a volatile memory and

wherein the method further comprises including access by the one or more CPUs to at least another portion of the volatile memory via the address map.

6. The method of claim 1 , wherein the method further comprises enabling, via software executing on a central processing unit (CPU) of the processing chip, the immutable hardware to perform the writing of the executable code update.

7. The method of claim 1 , wherein the method further comprises enabling, via software executing on a run-time programmable central processing unit (CPU) of the processing chip, the immutable hardware to perform the copying of the executable code update.

8. The method of claim 7 , wherein the enabling comprises issuing a command to a unified memory controller that causes the unified memory controller to set a state in a direct memory access (DMA) controller to perform the copying of the executable code update.

9. The method of claim 1 , wherein the copying of the executable code update comprises performing an integrity check on the executable code update.

10. The method of claim 1 , wherein the key is one of multiple keys.

11. The method of claim 1 , wherein the key is unusable for subsequent encryption operations.

12. A system, comprising:

a processing chip having immutable hardware and a network interface configured to establish a secure network connection;

a boot flash chip coupled to the processing chip configured to store executable code; and

external memory coupled to the processing chip, wherein the processing chip is configured to:

receive, via the secure network connection, executable code update to the executable code stored in the boot flash chip;

write, via the immutable hardware, the executable code update to a portion of external memory, wherein the portion of the external memory is only accessible to the immutable hardware of the processing chip;

copy, via the immutable hardware, the executable code update from the portion of the external memory to the boot flash chip; and

establish the secure network connection between the processing chip and an external entity possessing a public portion of a key with which the executable code update is encrypted, wherein a private portion of the key is unique to the processing chip and is stored solely within the processing chip, wherein the key is generated using a physically unclonable function in autonomous hardware in the processing chip.

13. A processing chip, comprising:

a network interface configured to establish a secure network connection; and

immutable hardware, wherein the processing chip is configured to:

receive, via the secure network connection, an executable code update to executable code associated with a boot flash chip;

write, via the immutable hardware, the executable code update to a portion of external memory that is only accessible to the immutable hardware of the processing chip; and

copy, via the immutable hardware, the executable code update from the portion of the external memory to the boot flash chip,

wherein the processing chip is configured to establish the secure network connection between the processing chip and an external entity possessing a public portion of a key with which the executable code update is encrypted; and

wherein a private portion of the key is unique to the processing chip and is stored solely within the processing chip, wherein the key is generated using a physically unclonable function in autonomous hardware in the processing chip.

14. The processing chip of claim 13 , wherein the private portion of the key is accessible solely by the immutable hardware.

15. The processing chip of claim 13 , wherein the processing chip comprises one or more central processing units (CPUs); and

wherein the processing chip is configured to securely boot the one or more CPUs by the immutable hardware performing operations comprising:

reading the executable code update from the boot flash chip;

decrypting the read executable code update using the private portion of the key; and

satisfying an initial instruction fetch of one of the CPUs with a portion of the decrypted executable code update.

16. The processing chip of claim 13 , wherein the processing chip comprises one or more central processing units (CPUs);

wherein the processing chip is configured to exclude access by the one or more CPUs to the portion of the external memory via an address map; and

wherein the one or more CPUs are configured to be securely booted by the immutable hardware to execute code read from the boot flash chip.

17. The processing chip of claim 13 , wherein the processing chip comprises a central processing unit (CPU); and

wherein the processing chip is configured to enable, via software executing on the CPU, the immutable hardware to perform the writing of the executable code update.

18. The processing chip of claim 13 , wherein the processing chip comprises a run-time programmable central processing unit (CPU); and

wherein the processing chip is configured to enable, via software executing on the run-time programmable CPU, the immutable hardware to perform the copying of the executable code update.

19. The processing chip of claim 13 , wherein the key is one of multiple keys.

20. The processing chip of claim 13 , wherein the key is unusable for subsequent encryption operations.