Display device and circuit for compensating for mobility characteristic of the display device
A display device includes an N-phase level shifter configured to receive an output cancellation signal, a first reference signal, and a second reference signal from a timing controller, and to output N sensing clock signals to a gate driver, and the gate driver configured to receive the N sensing clock signals from the N-phase level shifter, and to output N sensing output signals to first to n-th gate lines, wherein the N-phase level shifter is configured to receive the output cancellation signal having a number of pulses during a blank period, and the a is at least two.
1. A display device comprising:
an N-phase level shifter configured to:
receive an output cancellation signal, a first reference signal, and a second reference signal from a timing controller,
count a number of pulses in at least one of the first reference signal and the second reference signal, and
output a plurality of sensing clock signals to a gate driver based on inhibiting output of a number of clock signals corresponding to the number of pulses; and
wherein the gate driver is configured to receive the plurality of sensing clock signals from the N-phase level shifter and to output a plurality of sensing output signals to first to n-th gate lines,
wherein the N-phase level shifter is configured to inhibit output of a portion of the sensing clock signals of the plurality of sensing clock signals based on the number of pulses.
2. The display device of claim 1 , wherein gate lines configured to receive the plurality of sensing output signals are determined based on the output cancellation signal.
3. The display device of claim 2 , wherein the number of gate lines that are sensed during the blank period is equal to the first number.
4. The display device of claim 1 , wherein the output cancellation signal comprises a first pulse defining an interval for a first function of the N-phase level shifter, and a second pulse defining an interval for a second function of the N-phase level shifter.
5. The display device of claim 4 , wherein an order “b” of the sensing clock signal is determined on the basis of the number of pulses that are input during the first pulse, and the number of “b” is ranged between one and N.
6. The display device of claim 5 , wherein, when “b”−1 first reference signals and “b”−1 second reference signals are input during the first pulse, a “b”th sensing clock signal is determined.
7. The display device of claim 6 , wherein the N-phase level shifter is configured to receive one first reference signal and one second reference signal after the first pulse in order to generate the “b”th sensing clock signal.
8. The display device of claim 6 , wherein the N-phase level shifter is configured to output a Q-node charge signal before the “b”th sensing clock signal is output.
9. The display device of claim 5 , wherein an order “c” of the sensing clock signal is determined on the basis of the number of pulses that are input during the second pulse, and the number of “c” is ranged between one and N.
10. The display device of claim 9 , wherein, when “c”−1 first reference signals and “c”−1 second reference signals are input during the second pulse, a “c”th sensing clock signal is determined.
11. The display device of claim 10 , wherein the number of “b” and the number of “c” are different from each other.
12. The display device of claim 10 , wherein the N-phase level shifter is configured to receive one first reference signal and one second reference signal after the second pulse in order to generate the “c”th sensing clock signal.
13. The display device of claim 10 , wherein the N-phase level shifter is configured to output a Q-node discharge signal after the “c”th sensing clock signal is output.
14. The display device of claim 4 , wherein the first function corresponds to identification of gate lines for receiving a next clock signal.
15. The display device of claim 14 , wherein the second function corresponds to timing of pulses of the next clock signal.