Methods of reducing parasitic capacitance in semiconductor devices
A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.
1. A semiconductor structure, comprising:
a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), wherein the S/D feature is separated from the MG by a first air gap;
an S/D contact disposed over the S/D feature, wherein the S/D contact is separated from the MG by the first air gap, and wherein a bottom surface of the S/D contact is separated from a top surface of the S/D feature by a second air gap that is connected to the first air gap and laterally extends under the bottom surface of the S/D contact; and
a dielectric layer disposed over the first air gap.
2. The semiconductor structure of claim 1 , wherein the dielectric layer is a first dielectric layer, the semiconductor structure further comprising:
a gate spacer disposed between the first air gap and the MG, the gate spacer including a first dielectric material having a first dielectric constant; and
a second dielectric layer disposed between a sidewall of the S/D contact and the first air gap, the second dielectric layer including a second dielectric material having a second dielectric constant, wherein the first dielectric constant is different from the second dielectric constant.
3. The semiconductor structure of claim 2 , wherein the second dielectric constant is less than the first dielectric constant.
4. The semiconductor structure of claim 2 , wherein the second dielectric material is air.
5. The semiconductor structure of claim 1 , wherein the S/D contact includes a metal silicide layer and a metal conductive layer, wherein the metal silicide layer is disposed between the metal conductive layer and the S/D feature.
6. The semiconductor structure of claim 5 , wherein a width of the metal silicide layer is less than a width of the S/D feature.
7. The semiconductor structure of claim 1 , wherein the dielectric layer partially fills the first air gap.
8. A semiconductor structure, comprising:
a semiconductor fin disposed over a substrate;
a metal gate stack (MG) disposed over the semiconductor fin;
a source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the MG;
an S/D contact disposed over the S/D feature;
an air gap disposed between the S/D contact and the MG, wherein a first portion of the air gap is disposed along a sidewall of the S/D contact, wherein a second portion of the air gap is disposed along a sidewall of the S/D feature, and wherein a third portion of the air gap is disposed at an interface between the S/D contact and the S/D feature; and
a dielectric layer partially filling the first portion of the air gap.
9. The semiconductor structure of claim 8 , further comprising a silicide layer disposed between the S/D contact and the S/D feature, wherein a portion of the silicide layer is separated from a top surface of the S/D feature by the third portion of the air gap.
10. The semiconductor structure of claim 8 , wherein the dielectric layer is a first dielectric layer, the semiconductor structure further comprising a second dielectric layer disposed along the sidewall of the S/D contact, wherein the second dielectric layer is separated from the MG by the first portion of the air gap.
11. The semiconductor structure of claim 10 , wherein the first portion of the air gap has the same width as the second portion of the air gap.
12. The semiconductor structure of claim 8 , wherein the first portion of the air gap directly exposes the sidewall of the S/D contact.
13. The semiconductor structure of claim 12 , wherein the first portion of the air gap is wider than the second portion of the air gap.
14. The semiconductor structure of claim 8 , wherein the S/D contact includes cobalt.
15. A semiconductor structure, comprising:
a source/drain (S/D) feature disposed over a semiconductor fin;
a metal gate stack disposed adjacent to the S/D feature and separated from the S/D feature by a first air gap;
an S/D contact disposed over the S/D feature and separated from the metal gate stack by the first air gap;
a silicide layer disposed between the S/D feature and the S/D contact, wherein a portion of a bottom surface of the silicide layer is separated from the S/D feature along a vertical direction by a second air gap; and
a seal layer disposed over the first air gap.
16. The semiconductor structure of claim 15 , wherein the silicide layer is configured to have a curvature such that a middle portion of the silicide layer adjacent to the second air gap directly contacts the S/D feature.
17. The semiconductor structure of claim 15 , wherein the seal layer partially penetrates the first air gap.
18. The semiconductor structure of claim 15 , wherein the seal layer includes a first dielectric material, and wherein the semiconductor structure includes a second dielectric material disposed along a sidewall of the S/D contact.
19. The semiconductor structure of claim 18 , wherein the second dielectric material includes a low-k dielectric material.
20. The semiconductor structure of claim 15 , wherein a width of the first air gap adjacent to the S/D contact is greater than a width of the first air gap adjacent to the S/D feature.