Semiconductor package including thermal exhaust pathway

1. A semiconductor package comprising:

a wiring structure including signal wiring and a heat transfer wiring spaced apart from the signal wiring;

an active chip on the wiring structure;

a signal terminal disposed between the wiring structure and the active chip;

a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring;

a passive chip on the wiring structure;

a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring; and

a heat spreader on the passive chip,

wherein the passive chip is an electrically inactive dummy chip, and

wherein the heat transfer wiring is a single wiring in the wiring structure, and the plurality of first heat transferring terminals and the plurality of second heat transferring terminals are commonly connected to the single wiring.

2. The semiconductor package according to claim 1 , wherein the passive chip has a first thickness greater than a second thickness of the active chip.

3. The semiconductor package according to claim 1 , wherein vertical spacing between the passive chip and the heat spreader is less than vertical spacing between the active chip and the heat spreader.

4. The semiconductor package according to claim 1 , wherein the signal terminal, the first heat transferring terminal, and the second heat transferring terminal includes at least one of a solder ball, a conductive bump, an under bump metallurgy (UBM), a conductive pillar, a conductive lead, and a conductive pin.

5. The semiconductor package according to claim 1 , further comprising:

a first encapsulant between the wiring structure and the active chip and between the wiring structure and the passive chip,

wherein the first encapsulant includes an underfill material including a filler and a resin.

6. The semiconductor package according to claim 1 , further comprising:

a second encapsulant covers exposed portions of the wiring structure and exposed portions of side surfaces of the passive chip.

7. The semiconductor package according to claim 6 , wherein the second encapsulant covers exposed side surface of the active chip.

8. The semiconductor package according to claim 6 , wherein the second encapsulant extends between the exposed portions of the wiring structure and the heat spreader.

9. The semiconductor package according to claim 1 , further comprising:

a thermal interface material layer between the passive chip and the heat spreader.

10. The semiconductor package according to claim 9 , wherein the thermal interface material layer directly contacts an upper surface of the passive chip.

11. The semiconductor package according to claim 9 , wherein the thermal interface material layer directly contacts an upper surface of the active chip.

12. The semiconductor package according to claim 9 , wherein the thermal interface material layer extends between the active chip and the heat spreader.

13. The semiconductor package according to claim 1 , further comprising:

a through electrode extending through the passive chip between the second heat transferring terminal and the heat spreader.

14. A semiconductor package comprising:

a wiring structure including signal wiring and a heat transfer wiring;

an active chip on the wiring structure and connected to the signal wiring and the heat transfer wiring;

a passive chip on the wiring structure and connected to the heat transfer wiring; and

a heat spreader on the passive chip,

wherein the passive chip is an electrically inactive dummy chip, and

wherein the heat transfer wiring is a single wiring in the wiring structure, and wherein the active chip and the passive chip are commonly connected to the single wiring.

15. The semiconductor package according to claim 14 , wherein the wiring structure includes at least one of a redistribution layer, a printed circuit board, an interposer substrate, a logic chip, a buffer chip, a controller chip, an application processor chip, an interposer chip, a volatile memory chip and a non-volatile memory chip.

16. A semiconductor package comprising:

a redistribution layer including signal wiring and a heat transfer wiring;

an active chip on the redistribution layer;

a signal terminal between the redistribution layer and the active chip;

a first heat transferring terminal between the redistribution layer and the active chip and connected to the heat transfer wiring;

a passive chip on the redistribution layer;

a second heat transferring terminal disposed between the redistribution layer and the passive chip and connected to the heat transfer wiring;

a heat spreader on the passive chip;

an external terminal on a lower surface of the redistribution layer; and

an encapsulant disposed on the redistribution layer between the active chip and the heat spreader,

wherein the passive chip is an electrically inactive dummy chip, and

wherein the heat transfer wiring is a single wiring in the wiring structure, and wherein the first heat transferring terminal and the second heat transferring terminal are commonly connected to the single wiring.

17. The semiconductor package according to claim 16 , further comprising:

a thermal interface material layer between the passive chip and the heat spreader, and between the active chip and the heat spreader.

18. The semiconductor package according to claim 17 , wherein the thermal interface material layer directly contacts the passive chip.

19. The semiconductor package according to claim 16 , wherein the encapsulant includes an epoxy molding compound.