IP Library › Granted Patent US 12,009,378
Granted Patent B2
US 12,009,378 · App. 17/250,237 · Granted Jun 11, 2024

Solid-state imaging device and electronic apparatus

Inventor: Tetsuya Yamaguchi (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H01L27/14621H01L27/14627H04N25/70
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Quick Facts
Patent No.
US 12,009,378
App. No.
17/250,237
Granted
Jun 11, 2024
Kind
B2
Abstract

To provide a solid-state imaging device capable of improving image quality and an electronic apparatus equipped with the solid-state imaging device. There is provided a solid-state imaging device including a pixel array unit in which a plurality of pixels is one-dimensionally or two-dimensionally arrayed, the pixel array unit including a color filter and a semiconductor substrate for each pixel, a partition layer being formed between the color filters, the partition layer having a first width and a second width in order from a light incident side, the first width and the second width being different, and the second width being larger than the first width, and there is further provided an electronic apparatus equipped with the solid-state imaging device.

Claims (41)

1. A solid-state imaging device, comprising:

a pixel array unit that includes:

a plurality of pixels one-dimensionally or two-dimensionally arrayed;

color filters;

a semiconductor substrate; and

a partition layer between the color filters, wherein

the partition layer includes a first layer on a light incident side of the pixel array unit and a second layer on a semiconductor substrate side,

the first layer has a first width on the light incident side and a third width on the semiconductor substrate side,

the second layer has a fourth width on the light incident side and a second width on the semiconductor substrate side,

the second width is different from the first width,

the first layer includes a first metal layer and a first oxide film,

the first oxide film is on the first metal layer,

the second layer includes a second metal layer and a second oxide film, and

the second oxide film is on the second metal layer.

2. The solid-state imaging device according to claim 1 , wherein

the first layer on the light incident side is an uppermost layer and the second layer on the semiconductor substrate side is a lowermost layer.

3. The solid-state imaging device according to claim 1 , wherein

the partition layer includes a plurality of stages in which a stage on the light incident side is an uppermost stage and a stage on the semiconductor substrate side is a lowermost stage,

the uppermost stage has the first width on the light incident side and a fifth width on the semiconductor substrate side, and

the lowermost stage has a sixth width on the light incident side and the second width on the semiconductor substrate side.

4. The solid-state imaging device according to claim 1 , wherein

the partition layer includes two stages in which a stage on the light incident side is a first stage and a stage on the semiconductor substrate side is a second stage,

the first stage has the first width on the light incident side and a fifth width on the semiconductor substrate side, and

the second stage has a sixth width on the light incident side and the second width on the semiconductor substrate side.

5. The solid-state imaging device according to claim 1 , wherein a cross-sectional shape of the partition layer in a central portion of the pixel array unit is substantially right-left symmetrical.

6. The solid-state imaging device according to claim 1 , wherein a cross-sectional shape of the partition layer in a peripheral portion of the pixel array unit is right-left asymmetrical.

7. An electronic apparatus, comprising:

a solid-state imaging device that includes:

a pixel array unit that includes:

a plurality of pixels one-dimensionally or two-dimensionally arrayed;

color filters;

a semiconductor substrate; and

a partition layer between the color filters, wherein

the partition layer includes a first layer on a light incident side of the pixel array unit and a second layer on a semiconductor substrate side,

the first layer has a first width on the light incident side and a third width on the semiconductor substrate side,

the second layer has a fourth width on the light incident side and a second width on the semiconductor substrate side,

the second width is different from the first width,

the first layer includes a first metal layer and a first oxide film,

the first oxide film is on the first metal layer,

the second layer includes a second metal layer and a second oxide film, and

the second oxide film is on the second metal layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2020
From: YAMAGUCHI, TETSUYA
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 054818/0207 →
Priority Claims (1)
JP 2018-124550 · Jun 29, 2018 · national
Continuity (1)
Related Publication 20210126031A1 · Apr 29, 2021