Semiconductor device
A semiconductor device including a field insulating layer, a part of which protrudes upwardly in a vertical direction on an element isolation region between a first active region and a second active region may be provided.
1. A semiconductor device comprising:
a substrate including a first region and a second region, the second region being adjacent to the first region in a first horizontal direction;
a first active pattern extending in a second horizontal direction on the first region, the second horizontal direction being different from the first horizontal direction;
a second active pattern extending in the second horizontal direction on the second region, the second active pattern being spaced apart from the first active pattern in the first horizontal direction;
a field insulating layer surrounding at least a part of side walls of each of the first and second active patterns on the substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction on a boundary line between the first region and the second region;
a gate electrode extending in the first horizontal direction on the first and second active patterns;
a first source/drain region on at least one side of the gate electrode on the first active pattern;
a second source/drain region on at least one side of the gate electrode on the second active pattern; and
a source/drain contact electrically connecting the first source/drain region and the second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer between the first source/drain region and the second source/drain region, the second portion on the first portion,
wherein a lower surface of the first portion of the source/drain contact includes a recess which is recessed upwardly in the vertical direction, and
at least a part of the protrusion is inside the recess.
2. The semiconductor device of claim 1 , wherein an upper end of the protrusion is lower than an upper surface of the first active pattern that is in contact with the first source/drain region.
3. The semiconductor device of claim 1 , further comprising:
an interlayer insulating layer surrounding the first source/drain region and the source/drain contact on the field insulating layer; and
an etching stop layer being between the field insulating layer and the interlayer insulating layer, and being between the first source/drain region and the interlayer insulating layer.
4. The semiconductor device of claim 3 , wherein the etching stop layer is between the protrusion and the recess.
5. The semiconductor device of claim 3 , wherein the lower surface of the first portion of the source/drain contact is in contact with a part of the etching stop layer that is on an upper surface of the field insulating layer and adjacent to the protrusion.
6. The semiconductor device of claim 1 , wherein
an upper surface of the first active pattern that is in contact with the first source/drain region, and
an upper end of the protrusion is higher than the upper surface of the first active pattern.
7. The semiconductor device of claim 1 , wherein the first portion of the source/drain contact is in contact with the protrusion.
8. The semiconductor device of claim 1 , wherein the lower surface of the first portion of the source/drain contact is in contact with a part of an upper surface of the field insulating layer that is adjacent to the protrusion.
9. The semiconductor device of claim 1 , wherein
the field insulating layer includes,
a first upper surface between the first active pattern and the protrusion, and
a second upper surface between the second active pattern and the protrusion, and
the second upper surface of the field insulating layer is higher than the first upper surface of the field insulating layer.
10. The semiconductor device of claim 9 , wherein
the first portion of the source/drain contact includes a first lower surface and a second lower surface, the first lower surface facing the first upper surface of the field insulating layer, the second lower surface facing the second upper surface of the field insulating layer, and
the second lower surface of the first portion of the source/drain contact is higher than the first lower surface of the first portion of the source/drain contact.
11. The semiconductor device of claim 1 , wherein
the source/drain contact further includes a third portion that protrudes upwardly in the vertical direction from the second portion of the source/drain contact, and
a width of the third portion of the source/drain contact in the second horizontal is narrower than a width of the second portion of the source/drain contact in the first horizontal direction.
12. The semiconductor device of claim 1 , further comprising:
a first plurality of nanosheets stacked to be spaced apart from each other in the vertical direction on the first active pattern; and
a second plurality of nanosheets stacked to be spaced apart from each other in the vertical direction on the second active pattern,
wherein the gate electrode surrounds each of the first plurality of nanosheets and each of the second plurality of nanosheets.
13. A semiconductor device comprising:
a substrate;
a first active region extending in a first horizontal direction on the substrate;
a second active region extending in the first horizontal direction on the substrate, the second active region spaced apart from the first active region in a second horizontal direction, the second horizontal direction being different from the first horizontal direction;
an element isolation region between the first active region and the second active region;
a field insulating layer being on the element isolation region and surrounding at least a part of side walls of the first and second active regions, the field insulating layer including a protrusion protruding upwardly in a vertical direction;
a first source/drain region on the first active region;
a second source/drain region on the second active region;
a source/drain contact electrically connecting the first source/drain region and the second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer on the element isolation region, the second portion on the first portion;
an interlayer insulating layer surrounding the first source/drain region and the source/drain contact on the field insulating layer; and
an etching stop layer being between the field insulating layer and the interlayer insulating layer, and being between the first source/drain region and the interlayer insulating layer,
wherein at least a part of the protrusion extends into the first portion of the source/drain contact.
14. The semiconductor device of claim 13 , wherein
a lower surface of the first portion of the source/drain contact includes a recess being recessed upwardly in the vertical direction, and
at least a part of the protrusion is inside the recess.
15. The semiconductor device of claim 13 , wherein a lower surface of the first portion of the source/drain contact is lower than a lower surface of the first source/drain region.
16. The semiconductor device of claim 13 , wherein the etching stop layer is between the protrusion and the source/drain contact.
17. The semiconductor device of claim 13 , wherein the first portion of the source/drain contact is in contact with the protrusion.
18. The semiconductor device of claim 13 , wherein
the field insulating layer includes,
a first upper surface between the first active region and the protrusion, and
a second upper surface between the second active region and the protrusion, and
the second upper surface of the field insulating layer is higher than the first upper surface of the field insulating layer.
19. A semiconductor device comprising:
a substrate including an NMOS region and a PMOS region, the PMOS region adjacent to the NMOS region in a first horizontal direction;
a first active pattern extending in a second horizontal direction on the NMOS region, the second horizontal direction being different from the first horizontal direction;
a second active pattern extending in the second horizontal direction on the PMOS region, the second active pattern being spaced apart from the first active pattern in the first horizontal direction;
a field insulating layer surrounding at least a part of side walls of each of the first and second active patterns on the substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction on a boundary line between the NMOS region and the PMOS region;
a gate electrode extending in the first horizontal direction on the first and second active patterns;
a first source/drain region on at least one side of the gate electrode on the first active pattern;
a second source/drain region on at least one side of the gate electrode on the second active pattern;
a source/drain contact electrically connecting the first source/drain region and second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer between the first source/drain region and the second source/drain region, the second portion on the first portion;
an interlayer insulating layer surrounding the first source/drain region and the source/drain contact on the field insulating layer; and
an etching stop layer being between the field insulating layer and the interlayer insulating layer, and being between the first source/drain region and the interlayer insulating layer,
wherein an upper end of the protrusion is lower than an upper surface of the first active pattern that is in contact with the first source/drain region,
a lower surface of the first portion of the source/drain contact includes a recess that is recessed upwardly in the vertical direction, and
at least a part of the protrusion is in contact with the first portion of the source/drain contact inside the recess.
20. The semiconductor device of claim 19 , wherein the lower surface of the first portion of the source/drain contact is in contact with a part of an upper surface of the field insulating layer that is adjacent to the protrusion.