Integrated nanosheet field effect transistors and floating gate memory cells

1. A semiconductor device comprising: a nanosheet field effect transistor (FET) comprising a gate oxide layer; and

a floating gate memory cell comprising a tunneling oxide, a floating gate, a dielectric isolation layer, and a blocking oxide layer over a fin FET device.

2. The semiconductor device according to claim 1 , wherein the tunneling oxide and floating gate layers are disposed beneath a gate contact and the blocking oxide is disposed beneath and beside the gate contact.

3. The semiconductor device according to claim 1 , wherein the FET and floating gate memory cell are disposed at a common device level.

4. The semiconductor device according to claim 1 , wherein the floating gate memory comprises a vertical blocking oxide layer disposed adjacent to a control gate.

5. The semiconductor device according to claim 1 , wherein the FET further comprises a dielectric isolation layer.

6. The semiconductor device according to claim 1 , wherein the floating gate memory cell further comprises a plurality of fins.

7. A method of fabricating a semiconductor device, the method comprising:

forming a nanosheet stack and fin structures;

forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures;

forming dummy gate structures over the nanosheet stack and fin structures;

exposing the floating gate;

forming a blocking oxide layer over the floating gate; and

forming replacement metal gates.

8. The method according to claim 7 , further comprising forming an oxide layer adjacent to the blocking oxide layer and the nanosheet stack.

9. The method according to claim 7 , further comprising forming a dielectric isolation layer beneath a field effect transistor.

10. The method according to claim 7 , further comprising forming a dielectric isolation layer beneath a floating gate memory cell.

11. The method according to claim 7 , wherein the nanosheet stack and fin structures are formed at a common device level.

12. The method according to claim 7 , wherein the replacement metal gate is formed adjacent to vertical blocking oxide layers.

13. The method according to claim 8 , wherein the tunneling oxide and the floating gate layers are disposed beneath a gate contact and the blocking oxide is disposed beneath and beside the gate contact.

14. A method of fabricating a semiconductor device comprising a field effect transistor (FET) and a floating gate memory cell, the method comprising:

forming a nanosheet stack for the FET;

forming at least one fin structure for the floating gate memory;

forming tunneling oxide and floating gate layers over the fin structure;

forming dummy gate structures over the nanosheet stack and fin structures;

exposing the floating gate layer of the floating gate memory;

forming a blocking oxide layer over the floating gate; and

forming a replacement metal gate adjacent to the blocking oxide layer.

15. The method according to claim 14 , wherein the tunneling oxide and the floating gate layers are disposed beneath a gate contact and the blocking oxide is disposed beneath and beside the gate contact.

16. The method according to claim 14 , further comprising forming an oxide layer adjacent to the blocking oxide layer and the nanosheet stack.

17. The method according to claim 14 , further comprising forming a dielectric isolation layer beneath a field effect transistor.

18. The method according to claim 14 , further comprising forming a dielectric isolation layer beneath a floating gate memory cell.

19. The method according to claim 14 , wherein the nano sheet stack and fin structures are formed at a common device level.