IP Library Granted Patent US 12,010,931
Granted Patent B2
US 12,010,931 · App. 17/196,979 · Granted Jun 11, 2024

Resistive random-access memory (RRAM) device and forming method thereof

Inventors: Chia-Ching Hsu (Yunlin County, TW); Wang Xiang (Singapore, SG); Shen-De Wang (Hsinchu County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N70/841H10B63/845H10N70/021H10N70/066H10N70/8833
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Quick Facts
Patent No.
US 12,010,931
App. No.
17/196,979
Granted
Jun 11, 2024
Kind
B2
Abstract

A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.

Claims (17)

1. A resistive random-access memory (RRAM) device, comprising:

a bottom electrode line directly on a first metal structure;

a top electrode island disposed beside the bottom electrode line;

a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island; and

a second metal structure directly contacting the resistive material and the top electrode island.

2. The resistive random-access memory (RRAM) device according to claim 1 , further comprising:

a dielectric layer disposed on the bottom electrode lines, wherein the resistive material penetrates through the dielectric layer.

3. The resistive random-access memory (RRAM) device according to claim 2 , wherein the dielectric layer comprises a silicon nitride layer.

4. The resistive random-access memory (RRAM) device according to claim 1 , wherein the resistive material comprises transition-metal-oxide (TMO).

5. The resistive random-access memory (RRAM) device according to claim 1 , further comprising:

a cap layer between the first metal structure and the bottom electrode line.

6. The resistive random-access memory (RRAM) device according to claim 5 , wherein the cap layer has openings for the bottom electrode line physically connecting to the first metal structure.

7. The resistive random-access memory (RRAM) device according to claim 5 , wherein the cap layer comprises a nitrogen containing silicon carbide (SiCN) layer.

8. The resistive random-access memory (RRAM) device according to claim 1 , wherein the resistive material has a U-shape cross-sectional profile.

9. The resistive random-access memory (RRAM) device according to claim 1 , wherein the top electrode island has an I-shape cross-sectional profile or a T-shape cross-sectional profile.

10. The resistive random-access memory (RRAM) device according to claim 1 , further comprising:

a via disposed beside the RRAM cell, wherein two ends of the via contact the first metal structure and the second metal structure respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2021
From: HSU, CHIA-CHING; XIANG, WANG; WANG, SHEN-DE
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 055540/0961 →
Priority Claims (1)
TW 110103697 · Feb 1, 2021 · national
Continuity (1)
Related Publication 20220246845A1 · Aug 4, 2022
Cited By (1)
US 12,707,902