Method of screening non-volatile memory cells
A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M 1 , baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M 1.
1. A method for screening memory cells, comprising:
erasing the memory cells;
weakly programming the memory cells to a modified erased state;
performing a first read operation on the memory cells after the erasing and the weakly programming;
screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M 1 ;
baking the memory cells after the first read operation;
performing a second read operation on the memory cells after the baking; and
screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M 1 .
2. The method of claim 1 , wherein the margin read current threshold M 1 is greater than a read reference current used to determine an erased state of the memory cells during a nominal read operation.
3. The method of claim 1 , wherein:
each of the memory cells includes a control gate;
the performing of the first read operation includes applying a first read voltage to the control gates that is equal to a nominal read voltage for the control gates; and
the performing of the second read operation includes applying the first read voltage to the control gates.
4. The method of claim 1 , wherein:
each of the memory cells includes a control gate;
the performing of the first read operation includes applying a first read voltage to the control gates that is less than a nominal read voltage for the control gates; and
the performing of the second read operation includes applying a second read voltage to the control gates that is less than the nominal read voltage for the control gates and greater than the first read voltage.
5. A method for screening memory cells, comprising:
erasing the memory cells;
weakly programming the memory cells to a modified erased state;
performing a first read operation on the memory cells after the erasing and the weakly programming;
screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M 1 ;
baking the memory cells after the first read operation;
performing a second read operation on the memory cells after the baking; and
screening any of the memory cells that exhibit a read current during the second read operation below a margin read current threshold M 2 ;
wherein the margin read current thresholds M 1 and M 2 are greater than a read reference current used to determine an erased state of the memory cells during a nominal read operation, and the margin read current threshold M 2 is less than the margin read current threshold M 1 .
6. The method of claim 5 , wherein:
each of the memory cells includes a control gate;
the performing of the first read operation includes applying a first read voltage to the control gates that is less than a nominal read voltage for the control gates; and
the performing of the second read operation includes applying a second read voltage to the control gates that is less than the nominal read voltage for the control gates and greater than the first read voltage.
7. A method for screening memory cells, comprising:
strongly erasing the memory cells, wherein each of the memory cells includes a control gate;
performing a first read operation on the memory cells, after the strongly erasing, that includes applying a first read voltage to the control gates that is below a nominal read voltage for the control gates;
screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M 1 ;
weakly programming the memory cells to a modified erased state;
performing a second read operation on the memory cells, after the weakly programming, that includes applying a second read voltage to the control gates that is below a nominal read voltage for the control gates and greater than the first read voltage;
screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M 1 ;
baking the memory cells after the second read operation;
performing a third read operation on the memory cells, after the baking, that includes applying a third read voltage to the control gates that is below the nominal read voltage for the control gates and greater than the second read voltage; and
screening any of the memory cells that exhibit a read current during the third read operation below the margin read current threshold M 1 .
8. The method of claim 7 , wherein the margin read current threshold M 1 is greater than a read reference current used to determine an erased state of the memory cells during a nominal read operation.
9. A method for screening memory cells, comprising:
strongly erasing the memory cells, wherein each of the memory cells includes a control gate;
performing a first read operation on the memory cells, after the strongly erasing, that includes applying a first read voltage to the control gates that is below a nominal read voltage for the control gates;
screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M 1 ;
weakly programming the memory cells to a modified erased state;
performing a second read operation on the memory cells, after the weakly programming, that includes applying a second read voltage to the control gates that is below a nominal read voltage for the control gates and greater than the first read voltage;
screening any of the memory cells that exhibit a read current during the second read operation below a margin read current threshold M 2 ;
baking the memory cells after the second read operation;
performing a third read operation on the memory cells, after the baking, that includes applying a third read voltage to the control gates that is below the nominal read voltage for the control gates and greater than the second read voltage; and
screening any of the memory cells that exhibit a read current during the third read operation below a margin read current threshold M 3 ;
wherein the margin read current thresholds M 1 , M 2 and M 3 are greater than a read reference current used to determine an erased state of the memory cells during a nominal read operation, the margin read current threshold M 3 is less than the margin read current threshold M 2 , and the margin read current threshold M 2 is less than the margin read current threshold M 1 .