Vertically stacked semiconductor device including a hybrid bond contact junction circuit and methods of forming the same
View Patent ↗A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.
1. A semiconductor device comprising:
a first semiconductor die including a first contact;
a second semiconductor die including a side surface bonded to the first semiconductor die such that the second semiconductor die is perpendicular to the first semiconductor die, wherein the side surface comprises:
a dielectric layer comprising at least one of interlayer dielectric or intermetal dielectric; and
a second contact in the dielectric layer; and
a junction circuit contacting the first contact and the second contact and configured to connect the first semiconductor die to the second semiconductor die.
2. The semiconductor device of claim 1 , wherein the first semiconductor die comprises a first interface surface including the first contact,
wherein the second semiconductor die comprises a second interface surface formed in the side surface and including the second contact, and
wherein the junction circuit comprises a metal layer connecting the first contact to the second contact.
3. The semiconductor device of claim 2 , wherein the second contact comprises at least one of a metal contact, a metal bonding pad, a metal trench, a metal barrier layer and a metal via.
4. The semiconductor device of claim 2 , further comprising:
a bonding layer for bonding the second semiconductor die to the first semiconductor die, the junction circuit being formed in the bonding layer.
5. The semiconductor device of claim 4 , wherein the junction circuit comprises a bonding redistribution layer (RDL) circuit that is formed in the bonding layer.
6. The semiconductor device of claim 4 , wherein the junction circuit comprises a bonding pad that contacts the first contact in the first interface surface of the first semiconductor die.
7. A junction circuit comprising:
a bonding trench comprising a first surface and a second surface opposite the first surface, and a first end and a second end opposite the first end;
a bonding pad formed on the first surface of the bonding trench and at the first end of the bonding trench, wherein the bonding pad is configured to electrically couple the junction circuit with a first die; and
a bonding via formed on the second surface of the bonding trench and at the second end of the bonding trench, wherein the bonding via is configured to electrically couple the junction circuit with a second die.
8. The junction circuit of claim 7 , wherein the bonding trench extends longitudinally in a first direction, and a length of the bonding trench in the first direction is greater than a length of the bonding pad in the first direction.
9. The junction circuit of claim 8 , wherein the length of the bonding trench in the first direction is greater than a length of the bonding via in the first direction.
10. The junction circuit of claim 9 , wherein the length of the bonding pad in the first direction is greater than the length of the bonding via in the first direction.
11. The junction circuit of claim 8 , wherein a width of the bonding trench in a second direction perpendicular to the first direction is less than a width of the bonding pad in the second direction.
12. The junction circuit of claim 11 , wherein the width of the bonding trench in the second direction is greater than a width of the bonding via in the second direction.
13. The junction circuit of claim 12 , wherein the width of the bonding pad in the second direction is greater than the width of the bonding via in the second direction.
14. The junction circuit of claim 10 , wherein a thickness of the bonding trench in a third direction perpendicular to the first direction and the second direction is substantially the same as a thickness of the bonding pad in the third direction.
15. The junction circuit of claim 14 , wherein the thickness of the bonding trench in the third direction is substantially the same as a thickness of the bonding via in the third direction.
16. The junction circuit of claim 15 , wherein the thickness of the bonding pad in the third direction is substantially the same as the thickness of the bonding via in the third direction.
17. The junction circuit of claim 14 , wherein the bonding via comprises a substantially circular cross-section in a first plane, and each of the bonding trench and bonding pad comprises a substantially rectangular cross-section in the first plane.
18. The junction circuit of claim 7 , wherein each of the bonding trench, bonding pad and bonding via comprise at least one of copper, a copper alloy, aluminum and an aluminum alloy.
19. The junction circuit of claim 7 , wherein the bonding trench, bonding pad and bonding via comprise metal wiring layers of a bonding redistribution layer (RDL) circuit.
20. A method of making a semiconductor device, comprising:
forming a first semiconductor die including a first contact;
forming a second semiconductor die and forming a bonding layer on a side surface of the second semiconductor die, wherein the side surface includes:
a dielectric layer comprising at least one of interlayer dielectric or intermetal dielectric; and
a second contact in the dielectric layer;
forming a junction circuit in the bonding layer; and
bonding the bonding layer to the first semiconductor die such that the second semiconductor die is perpendicular to the first semiconductor die, and the junction circuit contacts the second contact in the dielectric layer of the side surface and connects the first semiconductor die to the second semiconductor die.