Optimized static random access memory
A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.
1. A memory cell comprising:
a substrate having a front side and a back side, wherein a transistor of the memory cell is formed on the front side, and wherein the back side is opposite of the front side;
a first interconnect layer on the front side to provide a bit line of the memory cell;
a second interconnect layer on the front side to provide a word line of the memory cell;
a third interconnect layer on the back side to provide a supply voltage to the memory cell; and
a fourth interconnect layer on the back side to provide a ground voltage to the memory cell,
wherein the first interconnect layer corresponds to a first bit line portion of the bit line that abuts a second bit line portion of an adjacent memory cell; and
wherein the third interconnect layer is wider than each of the first interconnect layer and the second interconnect layer.
2. The memory cell of claim 1 , wherein the first interconnect layer is a front side Metal 0 layer, the second interconnect layer is a front side Metal 1 layer, the third interconnect layer is a back side Metal 0 layer, and the fourth interconnect layer is a back side Metal 0 layer.
3. The memory cell of claim 1 , further comprising a first interconnect structure that connects the third interconnect layer to a first active region on the front side and a second interconnect structure that connects the fourth interconnect layer to a second active region on the front side.
4. The memory cell of claim 1 , wherein the second interconnect layer has a width that is less than the width of the first interconnect layer.
5. The memory cell of claim 1 , wherein the fourth interconnect layer is wider than the first interconnect layer and the second interconnect layer.
6. A memory device comprising:
a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a substrate having a front side and a back side, wherein a transistor of the memory cell is formed on the front side, and wherein the back side is opposite of the front side;
a first interconnect layer on the front side to provide a first bit line portion of the memory cell;
a second interconnect layer on the front side to provide a second bit line portion of the memory cell;
a third interconnect layer on the front side to provide a first word line of the memory cell; and
a fourth interconnect layer on the front side to provide a second word line of the memory cell;
a fifth interconnect layer on the back side to provide a ground voltage to the memory device,
wherein each of the first interconnect layer and the second interconnect layer has a width that is greater than the width of each of the third interconnect layer and the fourth interconnect layer;
wherein the first bit line portion abuts a first adjacent bit line portion of a first adjacent memory cell and the second bit line portion abuts a second adjacent bit line portion of a second adjacent memory cell; and
wherein the fifth interconnect layer is wider than each of the first interconnect layer, the second interconnect layer, the third interconnect layer, and the fourth interconnect layer.
7. The memory device of claim 6 , wherein each memory cell of the plurality of memory cells further comprises a first interconnect structure that connects the first interconnect layer to a first active region on the front side and a second interconnect structure that connects the second interconnect layer to a second active region on the front side.
8. The memory device of claim 6 , wherein each memory cell of the plurality of memory cells further comprises a first interconnect structure that connects the third interconnect layer to a first gate structure on the front side and a second interconnect structure that connects the fourth interconnect layer to a second gate structure on the front side.
9. The memory device of claim 6 , wherein the first interconnect layer is a front side Metal 0 layer, the second interconnect layer is a front side Metal 0 layer, the third interconnect layer is a front side Metal 1 layer, and the fourth interconnect layer is a front side metal 1 layer.
10. The memory device of claim 6 , wherein each memory cell of the plurality of memory cells further comprises:
a sixth interconnect layer on the back side to provide a supply voltage to the memory device.
11. The memory device of claim 10 , wherein each memory cell of the plurality of memory cells further comprises an interconnect structure that connects the sixth interconnect layer to an active region on the front side.
12. The memory device of claim 6 , wherein each memory cell of the plurality of memory cells further comprises an interconnect structure that connects the fifth interconnect layer to an active region on the front side.
13. The memory device of claim 10 , wherein the sixth interconnect layer is wider than each of the first interconnect layer, the second interconnect layer, the third interconnect layer, and the fourth interconnect layer.
14. A memory device comprising:
a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a substrate having a front side and a back side, wherein a plurality of active regions are formed on the front side, and wherein the back side is opposite of the front side;
a first interconnect layer on the back side to provide a supply voltage to the memory cell;
a second interconnect layer on the back side to provide a ground voltage to the memory cell;
a third interconnect layer on the front side to provide a bit line of the memory cell;
a fourth interconnect layer on the front side to provide a word line of the memory cell;
a first interconnect structure that connects the first interconnect layer to a first active region of the plurality of active regions on the front side; and
a second interconnect structure that connects the second interconnect layer to a second active region of the plurality of active regions on the front side;
wherein the third interconnect layer corresponds to a first bit line portion of the bit line that abuts a second bit line portion of an adjacent memory cell,
wherein the first interconnect layer is wider than each of the third interconnect layer and the fourth interconnect layer; and
wherein the second interconnect layer is wider than each of the third interconnect layer and the fourth interconnect layer.
15. The memory device of claim 14 , wherein each of the first interconnect structure and the second interconnect structure is a via structure.
16. The memory device of claim 14 , wherein a width of the third interconnect layer is greater the width of the fourth interconnect layer.
17. The memory device of claim 14 , wherein each memory cell of the plurality of memory cells further comprises a third interconnect structure that connects the third interconnect layer to the first active region of the plurality of active regions on the front side.
18. The memory device of claim 14 , wherein each memory cell of the plurality of memory cells further comprises a third interconnect structure that connects the fourth interconnect layer to a gate structure on the front side.