Static voltage drop (SIR) violation prediction systems and methods

1. A violation prediction system, comprising:

machine learning circuitry trained based on past data to predict the presence of violations in electronic device designs after routing has been performed, the machine learning circuitry configured to:

predict, based on the past data and a pre-routing layout of an electronic device design, whether one or more violations would be present in in the electronic device design due to routing of the pre-routing layout.

2. The system of claim 1 , further comprising:

a clock-tree synthesis (CTS) database configured to store CTS layout data associated with a CTS layout, the CTS layout being the pre-routing layout.

3. The system of claim 2 , further comprising:

a processed region database configured to store information associated with a plurality of CTS regions which exhibit static voltage (SIR) drop violations, wherein the machine learning circuitry is configured to predict whether one or more SIR drop violations would be present in the CTS layout based at least in part on the information associated with the plurality of CTS regions which exhibit SIR drop violations.

4. The system of claim 3 , further comprising:

a SIR drop database configured to store information associating SIR drop violations with at least one of a CTS layout or a CTS layout region,

wherein the machine learning circuitry is communicatively coupled to the SIR drop database, and the machine learning circuitry is configured to generate the information associated with the plurality of CTS regions which exhibit SIR drop violations based on the information stored in the SIR drop database.

5. The system of claim 1 , wherein the machine learning circuitry is configured to:

generate a static voltage (SIR) drop violation map indicating locations of predicted SIR drop violations in the pre-routing layout.

6. The system of claim 1 , further comprising:

a model bank which stores a plurality of machine learning models,

wherein the machine learning circuitry is communicatively coupled to the model bank, and the machine learning circuitry is configured to:

generate a first stage ensemble by selecting a first portion of the plurality of machine learning models based on a first similarity comparison between the pre-routing layout and the plurality of machine learning models; and

generate a second stage ensemble by selecting a second portion of the plurality of machine learning models based on a second similarity comparison between the pre-routing layout and the first portion of the plurality of machine learning models of the first stage ensemble.

7. The system of claim 6 wherein the machine learning circuitry is configured to generate a static voltage (SIR) drop map based on a comparison of the pre-routing layout with the second stage ensemble, the SIR drop map indicating predicted SIR drop values in the pre-routing layout.

8. The system of claim 7 wherein the machine learning circuitry is configured to compare the predicted SIR drop values with a threshold SIR drop value and predict whether one or more SIR drop violations would be present in the pre-routing layout due to routing of the pre-routing layout based on the comparison of the predicted SIR drop values with the threshold SIR drop value.

9. The system of claim 1 , further comprising:

clock tree cell adjustment circuitry configured to increase a spacing between clock cells of a region of the pre-routing layout, in response to the machine learning circuitry predicting that one or more static voltage (SIR) drop violations would be present in the region of the pre-routing layout due to the routing of the pre-routing layout.

10. A method, comprising:

receiving, by machine learning circuitry trained based on past data to predict the presence of static voltage (SIR) drop violations in electronic device designs after routing has been performed, layout data associated with a layout of a semiconductor device; and

predicting, by the machine learning circuitry and based on the past data, whether one or more SIR drop violations would be present in the layout due to routing of the layout.

11. The method of claim 10 , further comprising:

routing the layout in response to predicting that no SIR drop violations would be present in the layout due to routing of the layout.

12. The method of claim 10 , further comprising:

generating a SIR drop violation map indicating locations of predicted SIR drop violations in the layout.

13. The method of claim 12 wherein the predicting whether one or more SIR drop violations would be present in the layout due to routing of the layout includes:

comparing the predicted SIR drop values with a threshold SIR drop value; and

predicting that one or more SIR drop violations would be present in response to one or more of the predicted SIR drop values exceeding the threshold SIR drop value.

14. The method of claim 10 , further comprising:

selecting a first portion of a plurality of machine learning models based on a first similarity comparison between the layout and the plurality of machine learning models;

selecting a second portion of the plurality of machine learning models based on a second similarity comparison between the layout and the first portion of the plurality of machine learning models; and

generating a SIR drop map based on a comparison of the layout with the selected second portion of the plurality of machine learning models.

15. The method of claim 10 , further comprising:

adjusting the layout by increasing a spacing between clock cells of at least one region of the layout, in response to the machine learning circuitry predicting that one or more SIR drop violations would be present in the at least one region of the layout due to routing of the layout.

16. A method comprising:

training machine learning circuitry based on past data associated with electronic device designs after routing has been performed; and

predicting, by the machine learning circuitry, presence of violations associated with an electronic device design based on a pre-routing layout of the electronic device design and the past data.

17. The method of claim 16 wherein the training the machine learning circuitry includes extracting feature information associated with the plurality of electronic device designs.

18. The method of claim 17 , further comprising:

extracting feature information associated with the pre-routing layout for each of a plurality of regions of the pre-routing layout,

wherein the predicting whether one or more violations would be present in the pre-routing layout includes comparing the extracted feature information associated with the pre-routing layout with the extracted feature information associated with the plurality of electronic device designs.

19. The method of claim 16 , further comprising:

generating a first stage ensemble by selecting a first portion of a plurality of machine learning models based on a first similarity comparison between the pre-routing layout and the plurality of machine learning models; and

generating a second stage ensemble by selecting a second portion of the plurality of machine learning models based on a second similarity comparison between the pre-routing layout and the first portion of the plurality of machine learning models of the first stage ensemble,

wherein the predicting whether one or more static voltage (SIR) drop violations would be present in the pre-routing layout is based on the first similarity comparison and the second similarity comparison.

20. The method of claim 16 , further comprising:

adjusting the pre-routing layout by increasing a spacing between clock cells of the pre-routing layout, in response to predicting that one or more static voltage (SIR) drop violations would be present in the pre-routing layout; and

routing the adjusted layout.