Display clock signaling with reduced power consumption

1. An active-matrix display comprising:

a display area including a plurality of display pixels arranged in a matrix of a plurality of pixel rows and a plurality of pixel columns;

a gate driver circuit including a plurality of pixel row drivers, the plurality of pixel row drivers being configured as a shift register that sequentially and individually addresses the plurality of pixel rows of the display area, the plurality of pixel row drivers including:

a first set of multiple pixel row drivers configured to address a first set of multiple pixel rows of the plurality of pixel rows; and

a second set of multiple pixel row drivers configured to address a second set of multiple pixel rows of the plurality of pixel rows, wherein the second set of multiple pixels rows follows the first set of multiple pixel rows;

a first clock circuit configured to:

provide a first clock signal and a second clock signal to each pixel row driver in the first set of multiple pixel row drivers, when the gate driver circuit is addressing the first set of multiple pixel row drivers that are configured to address the first set of multiple pixel rows; and

inactivate the first clock signal and the second clock signal, when the gate driver circuit is addressing the second set of multiple pixel row drivers that are configured to address the second set of multiple pixel rows, the first clock circuit including at least one clock signal distribution circuit having a first input impedance; and

a second clock circuit configured to:

provide a third clock signal and a fourth clock signal to each pixel row driver in the second set of multiple pixel row drivers, when the gate driver circuit is addressing the second set of multiple pixel row drivers that are configured to address the second set of multiple pixel rows; and

inactivate the third clock signal and the fourth clock signal, when the gate driver circuit is addressing the first set of multiple pixel row drivers that are configured to address the first set of multiple pixel rows, the second clock circuit including at least one clock signal distribution circuit having a second input impedance that is matched with the first input impedance.

2. The active-matrix display of claim 1 , wherein:

the first clock circuit is configured to inactivate the first clock signal and the second clock signal, when the gate driver circuit is addressing the second set of multiple pixel row drivers, for a duration of multiple clock cycle time periods of the third clock signal and the fourth clock signal; and

the second clock circuit is configured to inactivate the third clock signal and the fourth clock signal, when the gate driver circuit is addressing the first set of multiple pixel row drivers, for a duration of multiple clock cycle time periods of the first clock signal and the second clock signal.

3. The active-matrix display of claim 1 , wherein:

the first clock circuit is configured to inactivate the first clock signal and the second clock signal, when the gate driver circuit is addressing the second set of multiple pixel row drivers, for a duration over which a plurality of pixel row drivers in the second set of multiple pixel row drivers scan their respective rows; and

the second clock circuit is configured to inactivate the third clock signal and the fourth clock signal, when the gate driver circuit is addressing the first set of multiple pixel row drivers, for a duration over which a plurality of pixel row drivers in the first set of multiple pixel row drivers scan their respective rows.

4. An electronic device comprising an active-matrix display, the active-matrix display including:

a display area including a plurality of display pixels arranged in a matrix of a plurality of pixel rows and a plurality of pixel columns;

a gate driver circuit including a plurality of pixel row drivers, the plurality of pixel row drivers being configured as a shift register that sequentially and individually addresses the plurality of pixel rows of the display area, the plurality of pixel row drivers including:

a first set of multiple pixel row drivers configured to address a first set of multiple pixel rows of the plurality of pixel rows; and

a second set of multiple pixel row drivers configured to address a second set of multiple pixel rows of the plurality of pixel rows, wherein the second set of multiple pixels rows follows the first set of multiple pixel rows;

a first clock circuit configured to:

provide a first clock signal and a second clock signal to each pixel row driver in the first set of multiple pixel row drivers, when the gate driver circuit is addressing the first set of multiple pixel row drivers that are configured to address the first set of multiple pixel rows; and

inactivate the first clock signal and the second clock signal, when the gate driver circuit is addressing the second set of multiple pixel row drivers that are configured to address the second set of multiple pixel rows, the first clock circuit including at least one clock signal distribution circuit having a first input impedance; and

a second clock circuit configured to:

provide a third clock signal and a fourth clock signal to each pixel row driver in the second set of multiple pixel row drivers, when the gate driver circuit is addressing the second set of multiple pixel row drivers that are configured to address the second set of multiple pixel rows; and

inactivate the third clock signal and the fourth clock signal, when the gate driver circuit is addressing the first set of multiple pixel row drivers that are configured to address the first set of multiple pixel rows, the second clock circuit including at least one clock signal distribution circuit having a second input impedance that is matched with the first input impedance.

5. A method of operating a display device with (i) a display area including a plurality of display pixels arranged in a matrix of a plurality of pixel rows and a plurality of pixel columns, (ii) a gate driver circuit including a plurality of pixel row drivers configured as a shift register that sequentially and individually addresses the plurality of pixel rows of the display area, the plurality of pixel row drivers including a first set of multiple pixel row drivers configured to address a first set of multiple pixel rows of the plurality of pixel rows, and a second set of multiple pixel row drivers configured to address a second set of multiple pixel rows of the plurality of pixel rows, with the second set of multiple pixels rows following the first set of multiple pixel rows, (iii) a first clock circuit including at least one clock signal distribution circuit having a first input impedance, and (iv) a second clock circuit including at least one clock signal distribution circuit having a second input impedance that is matched with the first input impedance, the method comprising:

providing, by the first clock circuit, a first clock signal and a second clock signal to each pixel row driver in the first set of multiple pixel row drivers, when the gate driver circuit is addressing the first set of multiple pixel row drivers that are configured to address the first set of multiple pixel rows;

inactivating the first clock signal and the second clock signal, when the gate driver circuit is addressing the second set of multiple pixel row drivers that are configured to address the second set of multiple pixel rows;

providing, by the second clock circuit, a third clock signal and a fourth clock signal to each pixel row driver in the second set of multiple pixel row drivers, when the gate driver circuit is addressing the second set of multiple pixel row drivers that are configured to address the second set of multiple pixel rows; and

inactivating the third clock signal and the fourth clock signal, when the gate driver circuit is addressing the first set of multiple pixel row drivers that are configured to address the first set of multiple pixel rows.