Spin-orbit-torque magnetoresistive random-access memory array
A spin-orbit torque magnetoresistive random-access memory device formed by forming an array of transistors, where a column of the array includes a source line contacting the source contact of each transistor of the column, forming a spin-orbit-torque (SOT) line contacting the drain contacts of the transistors of the row, and forming an array of unit cells, each unit cell including a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SOT line, where the SOT-MRAM cell stack includes a free layer, a tunnel junction layer, and a reference layer, a diode structure above and in electrical contact with the SOT-MRAM cell stack, an upper electrode disposed above and in electrical contact with the diode structure.
1. An MRAM (magnetoresistive random-access memory) structure comprising:
an array of spin-orbit-torque (SOT) magnetoresistive-random-access-memory (MRAM) cells, wherein:
a SOT-MRAM cell of the array comprises a transistor, a magnetic tunnel junction (MTJ), and a diode disposed above the MTJ, wherein the MTJ comprises a free layer, a tunnel junction layer, and a reference layer, each of the free layer, the tunnel junction layer, and the reference layer comprises a first width, the diode comprises a second width, and the second width is not equal to the first width, the diode comprises a two-dimensional diode junction material and an upper diode electrode layer comprising a sequence of W/TiO x /Ni layers;
a column of the array comprises a source line contacting a source contact of each transistor of the column, the source line disposed at a first metal layer of the MRAM structure; and
a row of the array comprises a SOT line contacting a drain contact of each transistor of the row, the SOT line disposed at a second metal layer of the MRAM structure.
2. The MRAM structure according to claim 1 , wherein the MTJ comprises a free layer adjacent to the SOT line.
3. The MRAM structure according to claim 1 , wherein the MTJ disposed above the transistor.
4. The MRAM structure according to claim 1 , wherein the SOT line is disposed perpendicular to the source line.
5. The MRAM structure according to claim 1 , wherein the diode structure is disposed in contact with an SOT-MRAM stack upper electrode.
6. An MRAM (magnetoresistive random-access memory) structure comprising:
an array of spin-orbit-torque (SOT) magnetoresistive-random-access-memory (MRAM) cells, wherein:
a SOT-MRAM cell of the array comprises a magnetic tunnel junction (MTJ), a diode disposed above the MTJ, and a single transistor, wherein the MTJ comprises a free layer, a tunnel junction layer, and a reference layer, each of the free layer, the tunnel junction layer, and the reference layer comprises a first width, the diode comprises a second width, and the second width is not equal to the first width, the diode comprises a two-dimensional diode junction material and an upper diode electrode layer comprising a sequence of W/TiO x /Ni layers;
a column of the array comprises a source line contacting a source contact of each transistor of the column, wherein the source line is disposed at a first metal layer of the MRAM structure;
the column comprises a bit line in contact with each diode of the column, wherein the bit line is disposed parallel to the source line and at a third metal layer of the MRAM structure; and
a row of the array comprises a SOT line contacting a drain contact of each transistor of the row, the SOT line disposed at a second metal layer of the MRAM structure.
7. The MRAM structure according to claim 6 , wherein the MTJ comprises a free layer adjacent to the SOT line.
8. The MRAM structure according to claim 6 , wherein the diode structure comprises a circular structure.
9. The MRAM structure according to claim 6 , wherein the diode structure comprises a square structure.
10. The MRAM structure according to claim 6 , wherein the diode structure is disposed in contact with an SOT-MRAM stack upper electrode.
11. An MRAM (magnetoresistive random-access memory) structure comprising:
an array of spin-orbit-torque (SOT) magnetoresistive-random-access-memory (MRAM) cells, wherein:
a SOT-MRAM cell of the array comprises a magnetic tunnel junction (MTJ), a diode disposed above the MTJ, and a single transistor, wherein the MTJ comprises a free layer, a tunnel junction layer, and a reference layer, each of the free layer, the tunnel junction layer, and the reference layer comprises a first width, the diode comprises a second width, and the second width is not equal to the first width, the diode comprises a two-dimensional diode junction material and an upper diode electrode layer comprising a sequence of W/TiOx/Ni layers;
a column of the array comprises a source line contacting a source contact of each transistor of the column, the source line disposed at a first metal layer of the MRAM structure;
a row of the array comprises a SOT line contacting a drain contact of each transistor of the row, the SOT line disposed at a second metal layer of the MRAM structure; and
the row of the array comprises a word line in contact with a gate of each transistor of the row, wherein the word line is disposed perpendicular to the source line.
12. The MRAM structure according to claim 11 , wherein the MTJ is disposed above the SOT line and comprises a free layer adjacent to the SOT line.
13. The MRAM structure according to claim 11 , wherein the MTJ is disposed above the transistor.
14. The MRAM structure according to claim 11 , wherein the SOT line is disposed perpendicular to the source line.
15. The MRAM structure according to claim 11 , wherein the diode structure is disposed in contact with an SOT-MRAM stack upper electrode.
16. An MRAM (magnetoresistive random-access memory) structure comprising:
an array of spin-orbit-torque (SOT) magnetoresistive-random-access-memory (MRAM) cells, wherein:
a SOT-MRAM cell of the array comprises a magnetic tunnel junction (MTJ), a diode and a single transistor, wherein the diode is disposed above the MTJ, wherein the MTJ comprises a free layer, a tunnel junction layer, and a reference layer, each of the free layer, the tunnel junction layer, and the reference layer comprises a first width, the diode comprises a second width, and the second width is not equal to the first width, the diode comprises a two-dimensional diode junction material and an upper diode electrode layer comprising a sequence of W/TiO x /Ni layers;
a column of the array comprises a source line contacting a source contact of each transistor of the column, the source line disposed at a first metal layer of the MRAM structure;
the column of the array comprises a bit line in contact with each diode of the column, the bit line disposed at a third metal layer of the MRAM structure;
a row of the array comprises a SOT line contacting a drain contact of each transistor of the row, and
the row of the array comprises a word line in contact with a gate of each transistor of the row.
17. The MRAM structure according to claim 16 , wherein source line and the bit line are disposed in parallel.
18. The MRAM structure according to claim 16 , wherein the SOT line is disposed perpendicular to the source line.
19. The MRAM structure according to claim 16 , wherein the word line is disposed perpendicular to the source line.
20. The MRAM structure according to claim 16 , wherein the source line is disposed at a first device level, the SOT line is disposed at a device second device level above the first level, and the bit line is disposed at a third device level above the second level.
21. A method of fabricating a semiconductor device, the method comprising:
forming an array of transistors, wherein:
a column of the array comprises a source line contacting a source contact of each transistor of the column;
forming a spin-orbit-torque (SOT) line contacting a drain contact of the transistors of a row of the array; and
forming an array of unit cells, each unit cell comprising a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SOT line, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, and a reference layer, a diode structure above and in electrical contact with the SOT-MRAM cell stack, an upper electrode disposed above and in electrical contact with the diode structure, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, and a reference layer, each of the free layer, the tunnel junction layer, and the reference layer comprises a first width, the diode structure comprises a second width, and the second width is not equal to the first width, the diode comprises a two-dimensional diode junction material and an upper diode electrode layer comprising a sequence of W/TiO x /Ni layers.
22. The method according to claim 21 , wherein the free layer is disposed adjacent to the SOT line.
23. The method according to claim 21 , further comprising forming a word line contacting a gate contact of each of the transistors of the row, wherein the word line is disposed parallel to the SOT line.
24. The method according to claim 21 , further comprising forming a bit line disposed above and in electrical contact with the upper electrodes of the unit cells of a column, wherein the bit line is disposed parallel to the source line.
25. The method according to claim 21 , further comprising forming the diode structure at process temperatures less than about 420C.