Image sensor and electronic system including the same
An image sensor includes a substrate having a pixel area in which a plurality of active areas is defined. A first transistor includes a first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.
1. An image sensor, comprising:
a substrate having a pixel area in which a plurality of active areas is defined;
a first transistor comprising a first gate electrode comprising a buried gate portion,
wherein the buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas; and
a second transistor comprising a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.
2. The image sensor of claim 1 , further comprising:
a first impurity region and a second impurity region in the first active area,
wherein the first impurity region and the second impurity region are spaced apart from each other in a lateral direction with the first gate electrode and the second gate electrode therebetween,
wherein the first impurity region and the second impurity region operate as a source and a drain of each of the first transistor and the second transistor.
3. The image sensor of claim 1 , wherein the first gate electrode further comprises an upper gate portion protruding in the vertical direction from a top surface of the buried gate portion to a level higher than a level of a front side surface of the substrate,
wherein the upper gate portion of the first gate electrode is spaced apart from the second gate electrode in a lateral direction, and the upper gate portion of the first gate electrode faces the second gate electrode in the lateral direction.
4. The image sensor of claim 1 , wherein the first transistor further comprises a first gate dielectric film between the first active area and the buried gate portion,
the second transistor further comprises a second gate dielectric film between the first active area and the second gate electrode and between the first gate electrode and the second gate electrode, and
a thickness of the second gate dielectric film is greater than a thickness of the first gate dielectric film.
5. The image sensor of claim 1 , wherein the first transistor further comprises a first gate dielectric film between the first active area and the buried gate portion,
the second transistor further comprises a second gate dielectric film between the first active area and the second gate electrode and between the first gate electrode and the second gate electrode, and
the second gate electrode is spaced apart from the buried gate portion in the vertical direction with the second gate dielectric film therebetween.
6. The image sensor of claim 1 , wherein a width of the buried gate portion of the first gate electrode is less than a width of the second gate electrode in a lateral direction.
7. The image sensor of claim 1 , wherein the first active area comprises a fin region protruding toward the buried gate portion, and
the buried gate portion comprises a protrusion covering a sidewall of the fin region.
8. The image sensor of claim 1 , further comprising:
a photodiode formed in the substrate,
wherein the first gate electrode and the second gate electrode overlap the photodiode in the vertical direction.
9. The image sensor of claim 1 , wherein each of the first gate electrode and the second gate electrode comprises doped polysilicon, and
a dopant concentration of the second gate electrode is higher than a dopant concentration of the buried gate portion of the first gate electrode.
10. The image sensor of claim 1 , further comprising:
a floating diffusion region formed in a second active area,
wherein the second active area is selected from the plurality of active areas and spaced apart from the first active area,
wherein the first gate electrode and the floating diffusion region are electrically connected to each other.
11. The image sensor of claim 1 , further comprising:
an upper gate portion constituting a portion of the first gate electrode,
wherein the upper gate portion protrudes in the vertical direction from a top surface of the buried gate portion to a level higher than a level of a front side surface of the substrate;
a floating diffusion region formed in a second active area selected from the plurality of active areas and spaced apart from the first active area;
a first contact plug connected to the upper gate portion;
a second contact plug connected to the floating diffusion region; and
a conductive line disposed on and connected to each of the first contact plug and the second contact plug.
12. An image sensor, comprising:
a substrate comprising a front side surface and a back side surface,
wherein the front side surface and the back side surface are opposite surfaces, and the substrate comprises a plurality of active areas defined at positions adjacent to the front side surface between the front side surface and the back side surface;
a photodiode formed in the substrate;
a source follower transistor disposed in a first active area selected from the plurality of active areas,
wherein the source follower transistor comprises a first gate electrode, the first gate electrode comprises a buried gate portion buried in the substrate and an upper gate portion in contact with the buried gate portion, and the upper gate portion overlaps a first region of the buried gate portion in a vertical direction;
a selection transistor comprising a second gate electrode overlapping a second region of the buried gate portion on the first active area in the vertical direction;
a transfer transistor formed in a second active area selected from the plurality of active areas;
a floating diffusion region formed in the second active area,
wherein the floating diffusion region is connected to the upper gate portion of the source follower transistor; and
a microlens covering the back side surface of the substrate.
13. The image sensor of claim 12 , further comprising:
a first impurity region and a second impurity region disposed in the first active area,
wherein the first impurity region and the second impurity region are spaced apart from each other in a lateral direction with the first gate electrode and the second gate electrode therebetween,
wherein the first impurity region and the second impurity region operate as a source and a drain of each of the source follower transistor and the selection transistor.
14. The image sensor of claim 12 , further comprising:
a first impurity region and a second impurity region disposed in the first active area,
wherein the first impurity region and the second impurity region are spaced apart from each other in a first lateral direction with the first gate electrode and the second gate electrode therebetween,
wherein the upper gate portion of the source follower transistor and the second gate electrode of the selection transistor are spaced apart from each other in a second lateral direction, the second lateral direction being perpendicular to the first lateral direction, and
a width of the buried gate portion is less than a width of the second gate electrode in the first lateral direction.
15. The image sensor of claim 12 , wherein the first active area comprises a fin region having a top surface and sidewalls facing the buried gate portion, and
the source follower transistor further comprises a gate dielectric film between the buried gate portion and the fin region.
16. The image sensor of claim 12 , wherein the buried gate portion overlaps the photodiode in the vertical direction.
17. The image sensor of claim 12 , wherein each of the buried gate portion and the upper gate portion of the source follower transistor and the second gate electrode of the selection transistor comprises doped polysilicon, and
a dopant concentration of each of the second gate electrode and the upper gate portion is higher than a dopant concentration of the buried gate portion.
18. The image sensor of claim 12 , wherein the selection transistor has a dual-gate-type structure in which channels are respectively formed on both sides of the buried gate portion.
19. The image sensor of claim 12 , wherein a portion of the upper gate portion and a portion of the second gate electrode are buried in the substrate.
20. An electronic system, comprising:
at least one camera module comprising an image sensor; and
a processor configured to process image data received from the at least one camera module,
wherein the image sensor comprises:
a substrate having a pixel area in which a plurality of active areas is defined;
a first transistor comprising a first gate electrode comprising a buried gate portion,
wherein the buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas; and
a second transistor comprising a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.