Semiconductor device with metal cap on gate

1. A device, comprising:

a gate structure over a substrate;

gate spacers on either side of the gate structure;

a gate helmet over the gate structure and the gate spacers;

a metal cap in the gate helmet over the gate structure; and

a gate contact over the metal cap, the gate contact forming an interface with the metal cap at a different level height than top segments of the gate spacers, wherein a distance between the level height of the interface and the level height of the top segments of the gate spacers is less than a height of the metal cap.

2. The device of claim 1 , wherein the interface formed by the gate contact and the metal cap is higher than the top segments of the gate spacers.

3. The device of claim 1 , wherein the metal cap comprises tungsten, titanium, or titanium nitride.

4. The device of claim 1 , wherein the metal cap forms an interface with the gate structure at a position lower than the top segments of the gate spacers.

5. The device of claim 1 , further comprising:

a source/drain contact spaced apart from the gate structure by one of the gate spacers, wherein a top segment of the source/drain contact is at a different level height than the interface formed by the gate contact and the metal cap.

6. The device of claim 5 , wherein the top segment of the source/drain contact is lower than the interface formed by the gate contact and the metal cap.

7. The device of claim 1 , wherein the gate helmet has a top segment at a different level height than the interface formed by the gate contact and the metal cap.

8. The device of claim 7 , wherein the top segment of the gate helmet is higher than the interface formed by the gate contact and the metal cap.

9. The device of claim 1 , wherein the metal cap has a lateral dimension and a vertical dimension greater than the lateral dimension.

10. The device of claim 1 , wherein one of the gate spacers has an outermost sidewall facing away from the gate structure and aligned with an outermost sidewall of the gate helmet.

11. A device, comprising:

a semiconductor fin;

source/drain contacts over the semiconductor fin;

a transistor gate spaced apart from one of the source/drain contacts at least in part by a spacer;

a dielectric layer over the transistor gate;

a metal cap in the dielectric layer; and

a gate contact over the metal cap, the gate contact having a sidewall flush with a sidewall of the metal cap, wherein the sidewall of the metal cap has a same slope as the sidewall of the gate contact.

12. The device of claim 11 , wherein the metal cap has a top surface higher than a top surface of the spacer.

13. The device of claim 11 , wherein the metal cap has a top surface lower than a top surface of the dielectric layer.

14. The device of claim 11 , wherein the dielectric layer overlaps a top surface of the spacer.

15. The device of claim 11 , wherein the dielectric layer non-overlaps the source/drain contacts.

16. The device of claim 11 , wherein the metal cap is tungsten.

17. A device, comprising:

a gate structure and a source/drain electrode over a substrate;

a gate spacer between the gate structure and the source/drain electrode, the gate spacer having a top segment higher than a top segment of the source/drain electrode;

a helmet layer over the gate spacer and the gate structure; and

a metal cap in the helmet layer over the gate structure, the metal cap having a top segment lower than a top segment of the helmet layer, wherein the top segment of the metal cap is higher than the top segment of the gate spacer by a distance smaller than a height of the metal cap.

18. The device of claim 17 , wherein the top segment of the metal cap is higher than the top segment of the source/drain electrode.

19. The device of claim 17 , wherein the helmet layer comprises SiN, SiO, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, ZrN, or amorphous silicon.

20. The device of claim 17 , wherein the source/drain electrode comprises cobalt, ruthenium or tungsten.