IP Library › Granted Patent US 12,026,009

Granted Patent B2

US 12,026,009 · App. 18/061,936 · Granted Jul 2, 2024

Quadrature clock generator with duty cycle corrector

Inventors: Chandra Shekar Reddy Ayya (Hyderabad, IN); Jae Won Choi (Irvine, CA)

Assignee: Synaptics Incorporated

G06F1/14 G06F1/08

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Quick Facts

Patent No.: US 12,026,009
App. No.: 18/061,936
Granted: Jul 2, 2024
Kind: B2

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Abstract

Quadrature clock generation circuits and techniques are disclosed. An example quadrature clock generator includes an in-phase (I) clock generation circuit to generate an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency, a quadrature phase (Q) clock generation circuit to generate a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency, and a control circuit to generate the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.

Claims (47)

1. A quadrature clock generator, comprising:

an in-phase (I) clock generation circuit to generate an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency;

a quadrature phase (Q) clock generation circuit to generate a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency; and

a control circuit to generate the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.

2. The quadrature clock generator of claim 1 , wherein the I clock generation circuit comprises a delay circuit configured to delay the reference clock signal.

3. The quadrature clock generator of claim 1 , wherein the Q clock generation circuit comprises a plurality of Q clock delay cells, each Q clock delay cell coupled to the rise time control signal and the fall time control signal.

4. The quadrature clock generator of claim 3 , wherein each Q clock delay cell comprises:

a first inverter having an input terminal, a power terminal, a ground terminal, and an output terminal;

a first transistor having a gate terminal coupled to the rise time control signal, a source terminal coupled to a supply voltage, and a drain terminal coupled to the power terminal of the first inverter; and

a second transistor having a gate terminal coupled to the fall time control signal, a source terminal coupled to a ground voltage, and a drain terminal coupled to the ground terminal of the first inverter.

5. The quadrature clock generator of claim 1 , wherein the control circuit includes a differential amplifier comprising:

a noninverting input terminal to receive an iqout average signal, the iqout average signal representing an average value of the I clock signal NAND an inverted Q clock signal;

an inverting input terminal to receive a signal representing 75% of a supply voltage of the quadrature clock generator;

a terminal to receive an output common mode voltage signal;

an inverting output to provide the fall time control signal; and

a noninverting output to provide the rise time control signal.

6. The quadrature clock generator of claim 5 , wherein the output common mode voltage signal is generated by an amplifier having an inverting input to receive a constant voltage signal representing 50% of the supply voltage, a noninverting input to receive a signal representing an average value of the Q clock signal, and an output terminal to provide the output common mode voltage signal.

7. The quadrature clock generator of claim 1 , wherein the control circuit is further configured to determine the rise time control signal and the fall time control signal based at least in part on a difference between a duty cycle of the Q clock signal and 50% of a supply voltage of the quadrature clock generator.

8. A quadrature clock generator, comprising:

an in-phase (I) clock generation circuit to generate an I clock signal by delaying a reference clock signal, the I clock signal and the reference clock signal each having a first frequency;

a quadrature phase (Q) clock generation circuit to generate a Q clock signal by delaying and adjusting a rise time and a fall time of the reference clock signal, the Q clock signal having the first frequency and having a phase offset of 90° with respect to the I clock signal; and

a control circuit to determine a rise time control signal and a fall time control signal for adjusting the rise time and fall time of the Q clock signal based at least in part on the I clock signal and the Q clock signal.

9. The quadrature clock generator of claim 8 , wherein the Q clock generation circuit comprises a plurality of Q clock delay cells, each Q clock delay cell coupled to the rise time control signal and the fall time control signal.

10. The quadrature clock generator of claim 8 , wherein the rise time delay increases when the rise time control signal increases, and the rise time delay decreases when the rise time control signal decreases.

11. The quadrature clock generator of claim 8 , wherein the fall time delay decreases when the fall time control signal increases, and the fall time delay increases when the fall time control signal decreases.

12. The quadrature clock generator of claim 8 , wherein the control circuit is configured to determine the rise time control signal and the fall time control signal based at least in part on the phase offset between the I clock signal and the Q clock signal.

13. The quadrature clock generator of claim 8 , wherein the control circuit is configured to determine the phase offset between the I clock signal and the Q clock signal based on a logic NAND between the I clock signal and an inverted Q clock signal.

14. The quadrature clock generator of claim 8 , wherein the control circuit is further configured to determine the rise time control signal and the fall time control signal based at least in part on a difference between a duty cycle of the Q clock signal and 50% of a supply voltage of the quadrature clock generator.

15. A dual rail quadrature clock generator, comprising:

an in-phase (I) clock generation circuit to generate a noninverted I clock signal and an inverted I clock signal based on a noninverted reference clock signal and an inverted reference clock signal, the noninverted I clock signal, the inverted I clock signal, the noninverted reference clock signal and the inverted reference clock signal each having a first frequency;

a quadrature phase (Q) clock generation circuit to generate a noninverted Q clock signal and an inverted Q clock signal based on the noninverted reference clock signal, the inverted reference clock signal, the noninverted I clock signal, and the inverted Q clock signal, wherein the noninverted Q clock signal and the inverted Q clock signal have the first frequency; and

a control circuit to generate a rise time control signal and a fall time control signal for adjusting a rise time and a fall time of the noninverted Q clock signal and the inverted Q clock signal, wherein the rise time control signal and the fall time control signal are generated based on the noninverted I clock signal and the inverted Q clock signal.

16. The dual rail quadrature clock generator of claim 15 , wherein the I clock generation circuit comprises a first I delay circuit configured to delay the noninverted reference clock signal to generate the noninverted I clock signal and a second I delay circuit configured to delay the inverted reference clock signal to generate the inverted I clock signal.

17. The dual rail quadrature clock generator of claim 15 , wherein the Q clock generation circuit comprises:

a plurality of first Q clock delay cells, each first Q clock delay cell configured to receive the noninverted reference clock signal, the rise time control signal and the fall time control signal; and

a plurality of second Q clock delay cells, each second Q clock delay cell configured to receive the inverted reference clock signal, the rise time control signal, and the fall time control signal.

18. The dual rail quadrature clock generator of claim 17 , wherein each first Q clock delay cell and each second Q clock delay cell comprises:

a first inverter having an input terminal, a power terminal, a ground terminal, and an output terminal;

19. The dual rail quadrature clock generator of claim 15 , wherein the control circuit includes a differential amplifier comprising:

a noninverting input terminal to receive an iqout average signal, the iqout average signal representing an average value of the I clock signal NAND an inverted Q clock signal;

an inverting input terminal to receive a signal representing 75% of a supply voltage;

a terminal to receive an output common mode voltage signal;

an inverting output to provide the fall time control signal; and

a noninverting output to provide the rise time control signal.

20. The dual rail quadrature clock generator of claim 19 , wherein the output common mode voltage signal is generated by an amplifier having an inverting input to receive a constant voltage signal representing 50% of the supply voltage, a noninverting input to receive a signal representing an average value of the Q clock signal, and an output terminal to provide the output common mode voltage signal.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2022

From: AYYA, CHANDRA SHEKAR REDDY; CHOI, JAE WON

To: SYNAPTICS INCORPORATED

Reel/Frame 061982/0470 →

Continuity (2)

Provisional Application 63306408 · Feb 3, 2022

Related Publication 20230244266A1 · Aug 3, 2023