Mitigating duty cycle distortion degradation due to device aging on high-bandwidth memory interface
Embodiments include a memory device with an improved circuit to mitigate degradation of memory devices due to aging. Memory device input/output pins include delay elements for adjusting the delay in each memory input/output signal path to synchronize the input/output signal paths with one another. Certain data patterns, including a long series of logic zero values or a long series of logic one values, can cause asymmetric degradation of transistors included in the delay elements. This asymmetric degradation can reduce the operating frequency of the memory device, leading to lower performance. The disclosed embodiments change the polarity of signals passing through the delay elements to mitigate the effects of asymmetric degradation resulting from these data patterns. As a result, the performance of memory devices is improved relative to prior approaches.
1. A method for generating control signals for a memory device, the method comprising:
detecting a first refresh command directed to the memory device;
in response to detecting the first refresh command, selecting a first polarity for a delay element of the memory device;
detecting a second refresh command directed to the memory device; and
in response to detecting the second refresh command, selecting a second polarity for the delay element of the memory device.
2. The method of claim 1 , wherein selecting the first polarity for the delay element comprises changing a logic level of a swap polarity signal from a first logic level to a second logic level.
3. The method of claim 2 , further comprising:
selecting a first input of a multiplexor when the logic level of the swap polarity signal is the first logic level; and
selecting a second input of the multiplexor when the logic level of the swap polarity signal is the second logic level,
wherein a first signal present on the first input of the multiplexor is an inverted version of a second signal present on the second input of the multiplexor.
4. The method of claim 1 , wherein the delay element is included in a data path associated with a data input/output pin of the memory device.
5. The method of claim 1 , wherein the delay element is included in a data path associated with at least one of a read data strobe pin or a write data strobe pin of the memory device.
6. The method of claim 1 , further comprising generating a swap pulse signal, wherein a leading edge of the swap pulse signal is delayed from a leading edge of the first refresh command by a controllable delay value.
7. The method of claim 6 , wherein the swap pulse signal has a pulse width based on a controllable pulse width value.
8. The method of claim 7 , wherein at least one of the controllable delay value or the controllable pulse width value is received from a software interface.
9. The method of claim 1 , further comprising disabling at least one of a read data strobe of the memory device or a write data strobe of the memory device while selecting the first polarity for the delay element.
10. The method of claim 1 , wherein the delay element includes at least one of a delay line or a phase interpolator.
11. A system, comprising:
a memory controller; and
a memory device comprising:
a delay element, and
a multiplexing circuit that:
detects a first refresh command received from the memory controller and directed to the memory device;
in response to detecting the first refresh command, selects a first polarity for a delay element of the memory device;
detects a second refresh command directed to the memory device; and
in response to detecting the second refresh command, selects a second polarity for the delay element of the memory device.
12. The system of claim 11 , wherein to select the first polarity for the delay element, the multiplexing circuit further changes a logic level of a swap polarity signal from a first logic level to a second logic level.
13. The system of claim 12 , wherein the multiplexing circuit further:
selects a first input of a multiplexor when the logic level of the swap polarity signal is the first logic level; and
selects a second input of the multiplexor when the logic level of the swap polarity signal is the second logic level,
wherein a first signal present on the first input of the multiplexor is an inverted version of a second signal present on the second input of the multiplexor.
14. The system of claim 11 , wherein the delay element is included in a data path associated with a data input/output pin of the memory device.
15. The system of claim 11 , wherein the delay element is included in a data path associated with at least one of a read data strobe pin or a write data strobe pin of the memory device.
16. The system of claim 11 , wherein the multiplexing circuit further generates a swap pulse signal, wherein a leading edge of the swap pulse signal is delayed from a leading edge of the first refresh command by a controllable delay value.
17. The system of claim 16 , wherein the swap pulse signal has a pulse width based on a controllable pulse width value.
18. The system of claim 17 , wherein at least one of the controllable delay value or the controllable pulse width value is received from a software interface.
19. The system of claim 11 , wherein the multiplexing circuit further disables at least one of a read data strobe of the memory device or a write data strobe of the memory device while selecting the first polarity for the delay element.
20. The system of claim 11 , wherein the delay element includes at least one of a delay line or a phase interpolator.