Vertical memory devices and methods for operating the same
This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.
1. A method for performing a programming operation on a memory device, wherein the memory device comprises a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, a source line under the pillar, and a bit line formed above the pillar, the method comprising:
applying a first positive voltage bias to the bottom select gate;
applying a second positive voltage bias to the word line;
applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias;
applying a ground voltage to the word line; and
applying the ground voltage to the bit line.
2. The method of claim 1 , wherein applying the ground voltage comprises performing the applying to the word line after the bit line reaches the third positive voltage bias.
3. The method of claim 1 , wherein applying the ground voltage to the bit line comprises performing the applying after the word line reaches the ground voltage.
4. The method of claim 1 , further comprising applying a fourth positive voltage bias to the plate line.
5. The method of claim 1 , wherein applying the first positive voltage bias comprises applying a voltage of between about 0.9 V and about 1.1 V to the bottom select gate.
6. A method for performing a programming operation on a memory device, wherein the memory device comprises a plate line, a bias gate above the plate line, a word line above the plate line, a pillar extending through the plate line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap, the method comprising:
applying a first positive voltage bias to the bias gate;
applying a second positive voltage bias to the word line;
applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias;
applying a ground voltage to the word line; and
applying the ground voltage to the bit line.
7. The method of claim 6 , wherein applying the ground voltage to the word line occurs after the bit line reaches the third positive voltage bias.
8. The method of claim 6 , wherein applying the ground voltage to the bit line occurs after the word line reaches the ground voltage.
9. The method of claim 6 , further comprising applying a fourth positive voltage bias to the plate line.
10. The method of claim 6 , wherein applying the first positive voltage bias comprises applying a voltage of between about 0.9 V and about 1.1 V to the bias gate.