One-time-programmable memory
View Patent ↗Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.
1. A one-time-programmable (OTP) memory cell, comprising:
an anti-fuse transistor;
a first select transistor operatively connected to the anti-fuse transistor;
a second select transistor operatively connected to the first select transistor, and
a bit line connected to a drain/source region of the second select transistor, wherein the bit line is configured to receive a negative bias voltage during a program operation.
2. The OTP memory cell of claim 1 , wherein the first select transistor and the second select transistor are operatively connected in parallel to a word line read signal line such that the first and the second select transistors form a cascaded select transistor.
3. The OTP memory cell of claim 2 , wherein the cascaded select transistor is connected in series with the anti-fuse transistor.
4. The OTP memory cell of claim 1 , wherein:
a first gate of the first select transistor is operatively connected to a first word line read signal line; and
a second gate of the second select transistor is operatively connected to a second word line read signal line.
5. The OTP memory cell of claim 4 , wherein the first word line read signal line is configured to receive a first bias voltage and the second word line read signal line is configured to receive a second bias voltage.
6. The OTP memory cell of claim 1 , wherein a drain/source region of the anti-fuse transistor is connected to a floating region.
7. A memory device, comprising:
a plurality of one-time-programmable (OTP) memory cells, each OTP memory cell comprising:
an anti-fuse transistor;
a first select transistor operatively connected to the anti-fuse transistor; and
a second select transistor operatively connected to the first select transistor, wherein:
a first word line read signal line is connected to a first gate of the first select transistor; and
a second word line read signal line is connected to a second gate of the second select transistor;
wherein:
the anti-fuse transistor comprises a third gate, a first dopant region that forms a first source/drain region, and a second dopant region that forms a second source/drain region, and
the memory device further comprises a first contact contacting the second dopant region the first contact configured to receive a bias voltage to activate an additional current path.
8. The memory device of claim 7 , wherein the second word line read signal line is connected to the first word line read signal line such that the first and the second select transistors form a cascaded select transistor.
9. The memory device of claim 7 , wherein the first word line read signal line is configured to receive a first bias voltage and the second word line read signal line is configured to receive a second bias voltage.
10. The memory device of claim 7 , wherein
the memory device further comprises:
a third dopant region extending from the first dopant region to under a portion of the third gate; and
a second contact contacting the first dopant region, the second contact configured to receive a bias voltage to activate an additional current path.
11. The memory device of claim 10 , further comprising a conductive element connecting the first contact to a second contact.
12. An electronic device, comprising:
a processing device;
a memory array operatively connected to the processing device, the memory array comprising:
a one-time-programmable (OTP) memory cell, comprising:
an anti-fuse transistor;
a first select transistor operatively connected in series to the anti-fuse transistor;
a second select transistor operatively connected to the first select transistor;
a first word line read signal line connected to a first gate of the first select transistor; and
a second word line read signal line connected to a second gate of the second select transistor and to the first word line read signal line such that the first and the second select transistors form a cascaded select transistor.
13. The electronic device of claim 12 , wherein:
the anti-fuse transistor comprises the first gate, a first dopant region that forms a first source/drain region, and a second dopant region that forms a second source/drain region;
the first select transistor comprises the second gate, the second dopant region that forms a third source/drain region, and a third dopant region that forms a fourth source/drain region; and
the OTP memory cell further comprises a fourth dopant region that connects to the first dopant region and extends partially under the first gate of the anti-fuse transistor, the additional fourth dopant region creating an additional current path for a read current.
14. The electronic device of claim 13 , wherein the OTP memory cell further comprises a halo region formed between the first dopant region and the fourth dopant region and adjacent the first dopant region.
15. The electronic device of claim 13 , wherein the OTP memory cell further comprises a halo region formed between the second dopant region and the third dopant region and adjacent the second dopant region.
16. The electronic device of claim 13 , wherein the first dopant region, the second dopant region, the third dopant region, and the fourth dopant region are formed with a dopant or dopants having a first conductivity type.
17. The OTP memory cell of claim 1 , wherein the first word line read signal line is electrically connected to the second word line read signal line.
18. The OTP memory cell of claim 1 , wherein the anti-fuse transistor comprises a first dopant region that forms a first source/drain region, and a second dopant region that forms a second source/drain region, and a first contact contacting the second dopant region, the first contact configured to receive a bias voltage to activate an additional current path.
19. The memory device of claim 7 , wherein the second select transistor is connected to a bit line.
20. The memory device of claim 7 , wherein the second select transistor includes a first source/drain region connected to a bit line, and a second source/drain region connected to a first source/drain region of the first select transistor.