Adjustable code rates and dynamic ECC in a data storage device with write verification

1. A data storage device, comprising:

a non-volatile storage medium;

a write channel circuit configured to, responsive to a host write operation:

calculate a first set of parity bits for a data unit; and

write the data unit and the first set of parity bits to the non-volatile storage medium; and

an error correction code processor circuit configured to, responsive to writing the data unit and the first set of parity bits to the non-volatile storage medium:

receive a first read signal for the data unit from the non-volatile storage medium;

decode, using a primary parity matrix and the first set of parity bits from the first read signal, the data unit;

selectively determine, responsive to decoding the data unit, an extended set of parity bits; and

store the extended set of parity bits for the data unit to an extended parity storage location.

2. The data storage device of claim 1 , wherein the error correction code processor circuit is further configured to:

receive a second read signal for the data unit from the non-volatile storage medium, wherein the second read signal includes the first set of parity bits;

receive the extended set of parity bits from the extended parity storage location;

decode, based on the first set of parity bits and the extended set of parity bits, the data unit from the second read signal; and

output a decoded data unit for the data unit.

3. The data storage device of claim 2 , wherein:

the first read signal is a write verification read signal for the data unit responsive to the host write operation; and

the second read signal is a read operation read signal responsive to a host read operation.

4. The data storage device of claim 3 , further comprising:

at least one processor configured to execute instructions to:

determine the extended parity storage location for the data unit; and

retrieve, during the host read operation, the extended set of parity bits from the extended parity storage location.

5. The data storage device of claim 1 , wherein:

the error correction code processor circuit comprises a plurality of parity matrices, the plurality of parity matrices including:

a primary parity matrix configured for a first code rate and first number of parity bits; and

a plurality of extended parity matrices configured for a plurality of additional code rates and incrementally extended numbers of parity bits;

the extended set of parity bits corresponds to:

an incrementally extended number of parity bits;

an adjusted code rate from the first code rate; and

a corresponding extended parity matrix from the plurality of extended parity matrices.

6. The data storage device of claim 5 , wherein:

the non-volatile storage medium comprises a plurality of memory cells;

the write channel circuit is further configured to write a plurality of data units to the plurality of memory cells; and

the error correction code processor circuit is further configured to:

selectively determine different code rates and different corresponding numbers of parity bits for the plurality of data units; and

decode the plurality of data units using the different corresponding numbers of parity bits and the plurality of parity matrices.

7. The data storage device of claim 1 , wherein the error correction code processor circuit is further configured to:

determine, based on decoding the data unit, a quality metric for the first read signal;

compare the quality metric to at least one code rate threshold value; and

select, based on the comparison of the quality metric to the at least on code rate threshold value, a number of extended parity bits for the extended set of parity bits corresponding to a desired code rate.

8. The data storage device of claim 7 , wherein:

the quality metric is a mutual information metric based on decoding the data unit; and

the at least one code rate threshold value includes a plurality of mutual information metric threshold values corresponding to incrementally adjusted code rates.

9. The data storage device of claim 1 , wherein the write channel circuit is further configured to:

write the data unit and the first set of parity bits to a first page in the non-volatile storage medium; and

write, responsive to the error correction code processor circuit determining the extended set of parity bits, the extended set of parity bits to a second page in the non-volatile storage medium.

10. The data storage device of claim 9 , wherein the second page in the non-volatile storage medium comprises reserved memory cells unallocated to a storage capacity of the data storage device.

11. A method comprising:

determining, responsive to a host write operation, a data unit and a first set of parity bits for the data unit;

writing, to a data storage location in a non-volatile storage medium, the data unit and the first set of parity bits;

reading, responsive to writing the data unit and the first set of parity bits and from the data storage location in the non-volatile storage medium, the data unit and the first set of parity bits in a first read signal;

decoding, using a primary parity matrix and the first set of parity bits from the first read signal, the data unit;

selectively determining, responsive to decoding the data unit, an extended set of parity bits; and

storing the extended set of parity bits for the data unit to an extended parity storage location.

12. The method of claim 11 , further comprising:

reading a second read signal for the data unit from the non-volatile storage medium, wherein the second read signal includes the data unit and the first set of parity bits;

retrieving the extended set of parity bits from the extended parity storage location;

decoding, based on the first set of parity bits and the extended set of parity bits, the data unit from the second read signal; and

outputting a decoded data unit for the data unit.

13. The method of claim 12 , wherein:

the first read signal is a write verification read signal for the data unit responsive to the host write operation; and

the second read signal is a read operation read signal responsive to a host read operation.

14. The method of claim 13 , further comprising:

determining the extended parity storage location for the data unit; and

retrieving, during the host read operation, the extended set of parity bits from the extended parity storage location.

15. The method of claim 12 , further comprising:

selecting, for decoding the data unit from the second read signal, a corresponding parity matrix from a plurality of parity matrices, wherein:

the plurality of parity matrices includes:

a primary parity matrix configured for a first code rate and first number of parity bits; and

a plurality of extended parity matrices configured for a plurality of additional code rates and incrementally extended numbers of parity bits; and

the extended set of parity bits corresponds to:

an incrementally extended number of parity bits;

an adjusted code rate from the first code rate; and

the corresponding extended parity matrix from the plurality of extended parity matrices.

16. The method of claim 15 , further comprising:

writing a plurality of data units to a plurality of memory cells in the non-volatile storage medium;

selectively determining different code rates and different corresponding numbers of parity bits for the plurality of data units; and

decoding, during read operations, the plurality of data units using the different corresponding numbers of parity bits and a parity matrix from the plurality of parity matrices.

17. The method of claim 11 , further comprising:

determining, based on decoding the data unit, a quality metric for the first read signal;

comparing the quality metric to at least one code rate threshold value; and

selecting, based on the comparison of the quality metric to the at least on code rate threshold value, a number of extended parity bits for the extended set of parity bits corresponding to a desired code rate.

18. The method of claim 17 , wherein:

the quality metric is a mutual information metric based on decoding the data unit; and

the at least one code rate threshold value includes a plurality of mutual information metric threshold values corresponding to incrementally adjusted code rates.

19. The method of claim 11 , further comprising:

writing the data unit and the first set of parity bits to a first page in the non-volatile storage medium; and

writing, responsive to determining the extended set of parity bits, the extended set of parity bits to a second page in the non-volatile storage medium.

20. A data storage device comprising:

a non-volatile storage medium;

means for determining, responsive to a host write operation, a data unit and a first set of parity bits for the data unit;

means for writing, to a data storage location in a non-volatile storage medium, the data unit and the first set of parity bits;

means for reading, responsive to writing the data unit and the first set of parity bits and from the data storage location in the non-volatile storage medium, the data unit and the first set of parity bits in a first read signal;

means for decoding, using a primary parity matrix and the first set of parity bits from the first read signal, the data unit;

means for selectively determining, responsive to decoding the data unit, an extended set of parity bits; and

means for storing the extended set of parity bits for the data unit to an extended parity storage location.