Memory device capable of minimizing bridge phenomenon of word lines and manufacturing method of the memory device

1. A memory device comprising:

a first gate conductive pattern disposed over a cell region and a contact region to extend horizontally from the cell region to the contact region, the first gate conductive pattern including a first horizontal part and a second horizontal part, which extend substantially in parallel to each other from the cell region to the contact region, and a third horizontal part connected to one end portion of the first horizontal part;

a first insulating pattern disposed between the first horizontal part and the second horizontal part of the first gate conductive pattern;

a second gate conductive pattern disposed substantially in parallel to the first gate conductive pattern under the first gate conductive pattern, the second gate conductive pattern including a first horizontal part and a second horizontal part, which extend substantially in parallel to each other from the cell region to the contact region, and a third horizontal part connected to one end portion of the first horizontal part of the second gate conductive pattern;

a second insulating pattern disposed between the first horizontal part and the second horizontal part of the second gate conductive pattern;

a first gate contact structure extending vertically over the contact region, the first gate contact structure being in contact with the first gate conductive pattern while penetrating the third horizontal part of the first gate conductive pattern; and

a second gate contact structure extending vertically over the contact region, the second gate contact structure being in contact with the second gate conductive pattern while penetrating the third horizontal part of the second gate conductive pattern,

wherein a length of the first gate conductive pattern extending to the contact region is shorter than that of the second gate conductive pattern extending to the contact region, and

wherein the first gate conductive pattern surrounds only a sidewall of the first insulating pattern which is a single insulating pattern corresponding to the first gate conductive pattern and the second gate conductive pattern surrounds only a sidewall of the second insulating pattern which is a single insulating pattern corresponding to the second gate conductive pattern.

2. The memory device of claim 1 ,

wherein one end portion of the second horizontal part of the first gate conductive pattern is connected to the third horizontal part of the first gate conductive pattern, and one end portion of the second horizontal part of the second gate conductive pattern is connected to the third horizontal part of the second gate conductive pattern.

3. The memory device of claim 1 ,

wherein the first gate contact structure extends vertically while penetrating the second insulating pattern.

4. The memory device of claim 3 ,

wherein the first gate contact structure is electrically and physically spaced apart from the second gate conductive pattern by the second insulating pattern.

5. The memory device of claim 1 , further comprising an interlayer insulating layer formed between the first gate conductive pattern and the second gate conductive pattern.

6. The memory device of claim 1 ,

wherein lengths of the first and second horizontal parts of the first gate conductive pattern are shorter than lengths of the first and second horizontal parts of the second gate conductive pattern.