Display device
A display device includes a first display region and a second display region having a lower pixel density than the first display region. A first pixel circuit in the first display region includes a first drive transistor, a first storage capacitor that stores a control voltage of the first drive transistor, and a first switch transistor that writes a data signal to the first storage capacitor. A second pixel circuit in the second display region includes a second drive transistor, a second storage capacitor that stores a control voltage of the second drive transistor, and a second switch transistor that writes a data signal to the second storage capacitor. A channel width of the second drive transistor is greater than a channel width of the first drive transistor. A channel width of the second switch transistor is greater than a channel width of the first switch transistor.
1. A display device, comprising:
a first display region; and
a second display region having a lower pixel density than the first display region;
wherein a first pixel circuit in the first display region includes:
a first drive transistor that controls a drive current amount to a light-emitting element;
a first storage capacitor that stores a control voltage of the first drive transistor; and
a first switch transistor that writes a data signal to the first storage capacitor,
wherein a second pixel circuit in the second display region includes:
a second drive transistor that controls a drive current amount to a light-emitting element;
a second storage capacitor that stores a control voltage of the second drive transistor; and
a second switch transistor that writes a data signal to the second storage capacitor,
wherein a channel width of the second drive transistor is greater than a channel width of the first drive transistor, and
wherein a channel width of the second switch transistor is greater than a channel width of the first switch transistor.
2. The display device according to claim 1 ,
wherein a gate potential fluctuation in the first drive transistor resulting from switching the first switch transistor from ON to OFF is equal to a gate potential fluctuation in the second drive transistor resulting from switching the second switch transistor from ON to OFF.
3. The display device according to claim 1 ,
wherein the first pixel circuit further includes a third switch transistor that electrically connects a gate to a drain of the first drive transistor when in an ON state,
wherein the second pixel circuit further includes a fourth switch transistor that electrically connects a gate to a drain of the second drive transistor when in an ON state, and
wherein a channel width of the fourth switch transistor is greater than a channel width of the third switch transistor.
4. The display device according to claim 3 ,
wherein a gate potential fluctuation of the first drive transistor resulting from switching the third switch transistor from ON to OFF is equal to a gate potential fluctuation in the second drive transistor resulting from switching the fourth switch transistor from ON to OFF.
5. The display device according to claim 1 ,
wherein the first drive transistor includes a first gate electrode,
wherein the second drive transistor includes a second gate electrode,
wherein a shape of the first gate electrode is the same as a shape of the second gate electrode, and
wherein a width of a semiconductor overlapping the second gate electrode is greater than a width of a semiconductor overlapping the first gate electrode.
6. The display device according to claim 5 ,
wherein distances from both edges of the first gate electrode to bend sections of a semiconductor layer are the same, and
wherein distances from both edges of the second gate electrode to bend sections of a semiconductor layer are the same.
7. The display device according to claim 5 ,
wherein a center axis of the first gate electrode matches a center axis of a channel of the first drive transistor in a plan view, and
wherein a center axis of the second gate electrode matches a center axis of a channel of the second drive transistor in a plan view.
8. The display device according to claim 7 , further comprising:
a first capacitor electrode, of the first storage capacitor, that covers the channel and the first gate electrode of the first drive transistor, and that has an opening;
a second capacitor electrode, of the second storage capacitor, that covers the channel and the second gate electrode of the second drive transistor, and that has an opening;
a first contact section that contacts the first gate electrode via the opening of the first capacitor electrode; and
a second contact section that contacts the second gate electrode via the opening of the second capacitor electrode,
wherein the center axis of the first gate electrode passes through a region where the first contact section contacts the first gate electrode, and
wherein the center axis of the second gate electrode passes through a region where the second contact section contacts the second gate electrode.
9. The display device according to claim 8 ,
wherein a minimum value of a distance between the first contact section and an opening edge of the first capacitor electrode is greater than a minimum value of a distance between an edge of the first gate electrode and an edge of the channel of the first drive transistor in a direction of the channel width of the first drive transistor, and
wherein a minimum value of a distance between the second contact section and an opening edge of the second capacitor electrode is greater than a minimum value of a distance between an edge of the second gate electrode and an edge of the channel of the second drive transistor in the direction of the channel width of the second drive transistor.