Transceiver device, driving method thereof, and display system including transceiver

1. A transceiver comprising:

a transmitter and a receiver connected to each other by a first line and a second line, wherein

the transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode, and

the transmitter encodes an original payload in the second mode to generate a first payload, and transmits a clock training pattern and the first payload through the first line and the second line,

wherein

the first line and the second line are used in a single-ended manner in the first mode, and

the first line and the second line are used in a differential manner in the second mode.

2. The transceiver of claim 1 , wherein the transmitter masks an internal clock signal used for delivery of the original payload during a masking period repeated at a preset cycle.

3. The transceiver of claim 2 , wherein the transmitter comprises:

a transmission controller which transmits the original payload based on the internal clock signal, and generates a first transmission request signal in the second mode;

a data transmitter which generates the internal clock signal, and transmits the clock training pattern and the first payload to the first line and the second line;

an encoder which encodes the original payload provided from the transmission controller into the first payload including an encoding key, and transmits the clock training pattern to the data transmitter in response to the first transmission request signal;

a clock counter which counts the internal clock signal, and generates a clock control signal in response to a preset count value; and

a clock controller which masks some of the internal clock signal based on the clock control signal, and provides a modified clock signal modified by the masking to the transmission controller and the encoder.

4. The transceiver of claim 3 , wherein the internal clock signal is output at a gate-off level during the masking period.

5. The transceiver of claim 4 , wherein an input of the original payload to the encoder is held during the masking period.

6. The transceiver of claim 3 , wherein

the transmission controller transmits the original payload to the encoder in synchronization with a gate-on level of the modified clock signal, and

the encoder receives the original payload in synchronization with the gate-on level of the modified clock signal.

7. The transceiver of claim 6 , wherein the encoder outputs the first payload to the data transmitter in synchronization with the gate-on level of the internal clock signal.

8. The transceiver of claim 3 , wherein, in the second mode, the encoder further generates a start pattern transmitted between the clock training pattern and the first payload, and further generates an end pattern transmitted after the first payload.

9. The transceiver of claim 8 , wherein the data transmitter sequentially transmits an HS-zero pattern and an HS-sync pattern before transmitting the clock training pattern, and sequentially transmits an HS-trail pattern and an HS-exit pattern after transmitting the end pattern.

10. The transceiver of claim 3 , wherein

the encoder provides a first transmission preparation signal to the transmission controller, and

the data transmitter provides a second transmission preparation signal to the encoder.

11. The transceiver of claim 10 , wherein

the first transmission request signal is activated and the first and second transmission preparation signals are deactivated in a first period, and

the encoder transmits the clock training pattern to the data transmitter in the first period.

12. The transceiver of claim 11 , wherein

the second transmission preparation signal is activated and the first transmission preparation signal is deactivated in a second period, and

the data transmitter transmits the clock training pattern to the first line and the second line in the second period.

13. A method of driving a transceiver including a transmitter and a receiver connected to each other by a first line and a second line, the method comprising:

transmitting signals having a first voltage range from the transmitter to the receiver in a first mode; and

transmitting signals having a second voltage range smaller than the first voltage range from the transmitter to the receiver in a second mode,

wherein the transmitting the signals having the second voltage range comprises:

transmitting a clock training pattern from the transmitter to the receiver through the first line and the second line; and

generating a first payload by encoding an original payload in an encoder included in the transmitter and transmitting the first payload from the transmitter to the receiver through the first line and the second line,

wherein

the first line and the second line are used in a single-ended manner in the first mode, and

the first line and the second line are used in a differential manner in the second mode.

14. The driving method of claim 13 , wherein the transmitting the first payload comprises:

counting an internal clock signal of the transmitter to mask some of the internal clock signal;

inputting the original payload to the encoder based on a modified clock signal modified by the masking;

encoding the original payload into the first payload using an encoding key; and

outputting the first payload from the encoder based on the internal clock signal.

15. The driving method of claim 14 , wherein the modified clock signal is output at a gate-off level during a masking period repeated at a preset cycle.

16. The driving method of claim 14 , wherein an input of the original payload to the encoder is held during a masking period repeated at a preset cycle.

17. The driving method of claim 14 , wherein encoding the original payload comprises:

generating a start pattern transmitted between the clock training pattern and the first payload and an end pattern transmitted after the first payload.

18. A display system comprising:

a processor which outputs image data;

a display module which displays an image based on the image data; and

a transceiver which transmits and receives data between the processor and the display module,

wherein

the transceiver comprises a transmitter and a receiver connected to each other by a first line and a second line,

the transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode,

the transmitter encodes an original payload in the second mode to generate a first payload, and transmits a clock training pattern and the first payload through the first line and the second line, and

the transmitter masks an internal clock signal used for delivery of the original payload during a masking period which is repeated at a preset cycle.