Optimizing place-and-routing using a random normalized polish expression

1. A method, comprising:

generating a first random normalized polish expression;

using at least one computer processor, using the first random normalized polish expression, generating a first place-and-route placement of cells for an integrated circuit design at least by placing a cell adjacent to a separate cell along a first direction and a second direction, wherein the first and the second directions are determined based at least in part upon an operator in the first random normalized polish expression;

for the first place-and-route placement, generating a plurality of interconnect routing paths between the cells of the first place-and-route placement according to at least the first and the second directions, wherein one or more of the plurality of interconnect routing paths are able to span across different interconnect layers; and

determining respective costs for the plurality of interconnect routing paths for the first place-and-route placement, wherein the plurality of interconnect routing paths comprise respective place-and-route solutions.

2. The method of claim 1 wherein

for a split in the first place-and-route placement, a first interconnect routing path comprises a first cell and a second cell with a space between the first and the second cells,

the first cell comprises first, second, third and fourth edges, the first edge is opposite of the third edge, and the second edge is opposite of the fourth edge,

the second cell comprises fifth, sixth, seventh, and eighth edges, the fifth edge is opposite to the seventh edge, and the sixth edge is opposite of the eighth edge, and

the space is between the second and the eighth edges and bounded by a first line passing through the first and fifth edges, and a second line passing through the third and the seventh edges.

3. The method of claim 2 wherein the first direction is horizontal, and the second direction is determined based at least in part upon the operator and the first direction.

4. The method of claim 2 wherein the first direction is vertical.

5. The method of claim 2 wherein the first interconnect routing path is routed from the second edge to the eighth edge, at least a first portion of the first interconnect routing path is in the space and extends parallel to the second and the eighth edges, and a second portion of the first interconnect routing path is in the space and extends transverse to the second and eighth edges.

6. The method of claim 1 wherein generating the first place-and-route solution comprises:

construing the first random normalized polish expression as a skewed slicing tree and beginning determining a respective place-and-route solution by placing and routing each pair of leaves in the skewed slicing tree.

7. The method of claim 6 wherein when the first direction is horizontal, a respective place-and-route solution comprises a first cell that is placed adjacent to a second cell, an interconnect line coupling the first and the second cells is in a vertical space with respect to the first and second cells, and the interconnect line comprises at least one 90-degree angle.

8. The method of claim 1 comprising:

using the at least one computer processor, calculating an intermediate cost for a candidate solution branch; and

based at least in part on the intermediate cost, pruning an unpromising candidate solution branch.

9. The method of claim 8 comprising:

while continue up a tree of the first place-and-route solution, combining child solutions.

10. The method of claim 9 comprising:

performing a simulated annealing on the first random normalized polish expression with a plurality of perturbations.

11. The method of claim 1 wherein a respective place-and-route solution comprises at least two cells and one interconnect coupling the two cells together and positioned in a space between the two cells.

12. The method of claim 1 wherein when the first direction is horizontal, a respective place-and-route solution comprises a first cell placed adjacent to a second cell with a space between the first and second cells, and an interconnect line coupling the first and second cells is placed in the space between the first and the second cells.

13. The method of claim 1 wherein a respective place-and-route solution comprises at least one interconnect line formed in a gap between a first cell and a second cell.

14. The method of claim 1 , wherein the first place-and-route solution comprises at least one interconnect line comprising at least one 90-degree angle to couple a first cell and a second cell.

15. The method of claim 1 , wherein

a respective place-and-route solution comprises first, second, third, and fourth cells placed horizontally with respect to each other, and a horizontal space exists between these cells, and

an interconnect coupling the first, second, third, and fourth cells is placed in a space vertically adjacent to these cells.

16. The method of claim 1

wherein a respective place-and-route solution comprises first and second cells placed vertically with respect to each other and third and fourth cells placed vertically with respect to each other, and the first and the second cells are placed horizontally with respect to the third and fourth cells, and

an interconnect coupling the first, the second, the third, and the fourth cells is placed in a space between the first and the second cells and between the third and the fourth cells.

17. The method of claim 1

a respective first place-and-route solution comprises a first interconnect coupling a first cell and a second cell, a second interconnect coupling the first and the second cells, and the first and second interconnect are formed on different interconnect layers.

18. A method comprising:

generating a first random normalized polish expression;

using at least one computer processor and the first random normalized polish expression, generating a first place-and-route placement of cells for an integrated circuit design at least by placing a cell adjacent to a separate cell along a first direction and a second direction, wherein the first and the second directions are determined based at least in part upon an operator in the first random normalized polish expression;

for the first place-and-route placement, generating a plurality of interconnect routing paths between the cells of the first place-and-route placement according to at least the first and the second directions, wherein one or more of the plurality of interconnect routing paths are able to span across different interconnect layers; and

determining respective costs for the interconnect routing paths for the first place-and-route placement, wherein the plurality of interconnect routing paths comprise respective place-and-route solutions,

wherein a first respective place-and-route solution comprises at least one first interconnect line formed in a gap between a first cell and second cell,

a second respective place-and-route solution comprises at least one second interconnect line having a 90-degree turn coupling the first and the second cells, and

a third respective place-and-route solution comprises at least one third interconnect line having at least two 90-degree turns coupling the first and the second cells, and

calculating respective cost functions for the first, the second, and the third place-and-route solutions;

based at least in part upon the respective cost functions, selecting one of the first, the second, and the third place-and-route solutions.

19. The method of claim 18 ,

wherein calculating the respective cost functions comprises considering a wire length of the first, the second, or the third interconnect coupling the first and the second cells, and the wire length includes a length of a gap between the first and the second cells.

20. A method comprising:

generating a first random normalized polish expression;

using at least one computer processor, using the first random normalized polish expression, generating a first place-and-route placement of cells for an integrated circuit design at least by placing a cell adjacent to a separate cell along a first direction and a second direction, wherein the first and the second directions are determined based at least in part upon an operator in the first random normalized polish expression;

for the first place-and-route placement, generating a plurality of interconnect routing paths between the cells of the first place-and-route placement according to at least the first and the second directions, wherein one or more interconnect routing paths on are able to span across different interconnect layers;

determining respective interconnection costs for the plurality of interconnect routing paths for the first place-and-route placement, wherein the plurality of interconnect routing paths comprise respective place-and-route solutions;

generating a second random normalized polish expression;

using the at least one computer processor and the second random normalized polish expression, generating a second place-and-route solution for the integrated circuit design and a solution cost of the first place-and-route solution, wherein the solution cost is generated based at least in part on a wire length of an interconnect in a space between two cells; and

placing at least two of the cells for the second place-and-route solution adjacent to each other in another direction based at least in part on the second random normalized polish expression.