OLED display panel and OLED display device

1. An organic light emitting diode (OLED) display panel, comprising a display region and a non-display region surrounding the display region, wherein the non-display region comprises a bonding region, a first fan-out line region, a bending region, and a second fan-out line region, the bending region is arranged between the first fan-out line region and the second fan-out line region, the first fan-out line region and the second fan-out line region both comprise a plurality of fan-out data lines, the bonding region is provided with an integrated circuit chip and a plurality of pads, and the fan-out data lines are connected to the pads through the bonding region,

wherein a bonding test region is arranged between the bonding region and the first fan-out line region, a bonding test circuit is disposed in the bonding test region, and the bonding test circuit is configured to detect whether the fan-out data line passing through the bonding region is abnormal; and

wherein the bonding test circuit comprises a first test input line, a second test input line, a test data line, and a plurality of thin film transistors (TFTs), and the plurality of TFTs are arranged along a first direction, wherein materials of the fan-out data line, the first test input line, the second test input line, and the test data line are the same as a material of a source/drain of the TFT.

2. The OLED display panel according to claim 1 , wherein a test data voltage of the test data line ranges from 2V to 5V.

3. The OLED display panel according to claim 1 , wherein the first test input line and the second test input line are configured to control an on/off state of the plurality of TFTs, and the test data line is configured to input test data signals to the bonding region.

4. The OLED display panel according to claim 1 , wherein the plurality of TFTs are p-type metal oxide semiconductor (PMOS) devices.

5. The OLED display panel according to claim 4 , wherein the plurality of TFTs comprise a first-type TFT and a second-type TFT, a gate of the first-type TFT is connected to the first test input line, a source of the first-type TFT is connected to the test data line, and a drain of the first-type TFT is connected to the fan-out data line; and a gate of the second-type TFT is connected to the second test input line, a source of the second-type TFT is connected to the fan-out data line, and a drain of the second-type TFT is connected to the fan-out data line.

6. The OLED display panel according to claim 5 , wherein when the OLED display panel is in a module test stage, a voltage of the first test input line is a high-level voltage, the first-type TFT is turned off, a voltage of the second test input line is a low-level voltage, the second-type TFT is turned on, and the fan-out data line inputs a first data signal to the bonding region; when the OLED display panel is in a bonding test stage, the voltage of the first test input line is a low-level voltage, the first-type TFT is turned on, the voltage of the second test input line is a high-level voltage, the second-type TFT is turned off, and the test data line inputs a second data signal to the bonding region.

7. The OLED display panel according to claim 6 , wherein when the OLED display panel has a vertical line defect during the module test stage, but has no vertical line defects during the bonding test stage, the fan-out data line located in the bonding region is in an abnormal state.

8. An OLED display device, comprising an OLED display panel, wherein the OLED display panel comprises a display region and a non-display region surrounding the display region, wherein the non-display region comprises a bonding region, a first fan-out line region, a bending region, and a second fan-out line region, the bending region is arranged between the first fan-out line region and the second fan-out line region, the first fan-out line region and the second fan-out line region are both provided with a plurality of fan-out data lines, the bonding region is provided with an integrated circuit chip and a plurality of pads, and the fan-out data lines are connected to the pads through the bonding region,

wherein a bonding test region is arranged between the bonding region and the first fan-out line region, a bonding test circuit is disposed in the bonding test region, and the bonding test circuit is configured to detect whether the fan-out data line passing through the bonding region is abnormal; and

wherein the bonding test circuit comprises a first test input line, a second test input line, a test data line, and a plurality of thin film transistors (TFTs), and the plurality of TFTs are arranged along a first direction, wherein materials of the fan-out data line, the first test input line, the second test input line, and the test data line are the same as a material of a source/drain of the TFT.

9. The OLED display device according to claim 8 , wherein a test data voltage of the test data line ranges from 2V to 5V.

10. The OLED display device according to claim 8 , wherein the first test input line and the second test input line are configured to control an on/off state of the plurality of TFTs, and the test data line is configured to input test data signals to the bonding region.

11. The OLED display device according to claim 8 , wherein the plurality of TFTs are p-type metal oxide semiconductor (PMOS) devices.

12. The OLED display device according to claim 11 , wherein the plurality of TFTs comprise a first-type TFT and a second-type TFT, a gate of the first-type TFT is connected to the first test input line, a source of the first-type TFT is connected to the test data line, and a drain of the first-type TFT is connected to the fan-out data line; and a gate of the second-type TFT is connected to the second test input line, a source of the second-type TFT is connected to the fan-out data line, and a drain of the second-type TFT is connected to the fan-out data line.

13. The OLED display device according to claim 12 , wherein when the OLED display panel is in a module test stage, a voltage of the first test input line is a high-level voltage, the first-type TFT is turned off, a voltage of the second test input line is a low-level voltage, the second-type TFT is turned on, and the fan-out data line inputs a first data signal to the bonding region; when the OLED display panel is in a bonding test stage, the voltage of the first test input line is a low-level voltage, the first-type TFT is turned on, the voltage of the second test input line is a high-level voltage, the second-type TFT is turned off, and the test data line inputs a second data signal to the bonding region.

14. The OLED display device according to claim 13 , wherein when the OLED display panel has a vertical line defect during the module test stage, but has no vertical line defects during the bonding test stage, the fan-out data line located in the bonding region is in an abnormal state.

15. An organic light emitting diode (OLED) display panel, comprising a display region and a non-display region surrounding the display region, wherein the non-display region comprises a bonding region, a first fan-out line region, a bending region, and a second fan-out line region, the bending region is arranged between the first fan-out line region and the second fan-out line region, the first fan-out line region and the second fan-out line region both comprise a plurality of fan-out data lines, the bonding region is provided with an integrated circuit chip and a plurality of pads, and the fan-out data lines are connected to the pads through the bonding region,

wherein a bonding test region is arranged between the bonding region and the first fan-out line region, a bonding test circuit is disposed in the bonding test region, and the bonding test circuit is configured to detect whether the fan-out data line passing through the bonding region is abnormal;

wherein the bonding test circuit comprises a first test input line, a second test input line, a test data line, and a plurality of thin film transistors (TFTs), the plurality of TFTs are arranged along a first direction, and the plurality of TFTs are p-type metal oxide semiconductor (PMOS) devices; and

wherein the plurality of TFTs comprise a first-type TFT and a second-type TFT, a gate of the first-type TFT is connected to the first test input line, a source of the first-type TFT is connected to the test data line, and a drain of the first-type TFT is connected to the fan-out data line; and a gate of the second-type TFT is connected to the second test input line, a source of the second-type TFT is connected to the fan-out data line, and a drain of the second-type TFT is connected to the fan-out data line.

16. The OLED display panel according to claim 15 , wherein a test data voltage of the test data line ranges from 2V to 5V.

17. The OLED display panel according to claim 15 , wherein the first test input line and the second test input line are configured to control an on/off state of the plurality of TFTs, and the test data line is configured to input test data signals to the bonding region.

18. The OLED display panel according to claim 15 , wherein when the OLED display panel is in a module test stage, a voltage of the first test input line is a high-level voltage, the first-type TFT is turned off, a voltage of the second test input line is a low-level voltage, the second-type TFT is turned on, and the fan-out data line inputs a first data signal to the bonding region; when the OLED display panel is in a bonding test stage, the voltage of the first test input line is a low-level voltage, the first-type TFT is turned on, the voltage of the second test input line is a high-level voltage, the second-type TFT is turned off, and the test data line inputs a second data signal to the bonding region.