Memory device and operation method thereof for performing multiply accumulate operation

1. A memory device comprising:

a memory array including a plurality of memory cells, the memory cells storing a plurality of weights, the memory cells being coupled to a plurality of word lines, a plurality of first signal lines and a plurality of second signal lines, the plurality of memory cells are controlled by the plurality of word lines;

a local signal line decoder coupled to the memory array and a global signal line; and a conversion unit coupled to the local signal line decoder and the global signal line;

wherein

in performing a multiply accumulate (MAC) operation, a plurality of inputs are input into the memory cells via the word lines;

the memory cells output a plurality of cell currents to the second signal lines based on the weights of the memory cells;

the cell currents on each of the second signal lines are summed into a plurality of signal line currents and input into the local signal line decoder;

the local signal line decoder sums the signal line currents into a global signal line current;

the conversion unit converts the global signal line current from the local signal line decoder into an output, wherein the output represents a MAC operation result of the inputs and the weights,

in presenting x-level weight of a weight unit comprising at least one memory cell among the plurality of memory cells, the at least one memory cell of the weight unit being coupled to a single one of the word lines, and the weight unit receiving a single input of the plurality of inputs via the single one of the word lines, a number of the second signal lines coupled to the same conversion unit is expressed as: Q=2 x −1, x and Q are both positive integers, Q is the number of the second signal lines coupled to the same conversion unit; and

the memory cells are single-level storage cells,

in performing the MAC operation, a plurality of transistors of the local signal line decoder are turned on.

2. The memory device according to claim 1 , wherein each of the plurality of transistors of the local signal line decoder includes a first terminal coupled to one among the second signal lines, a second terminal coupled to the global signal line and an input of the conversion unit, and a control terminal for receiving a control signal.

3. The memory device according to claim 1 , wherein the conversion unit is an analog-to-digital converter (ADC).

4. An operation method for a memory device, the operation method comprising:

in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of word lines, the plurality of memory cells are controlled by the plurality of word lines;

outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells;

summing the cell currents on each of the second signal lines into a plurality of signal line currents;

summing the signal line currents into a global signal line current;

converting the global signal line current into an output by a conversion unit, wherein the output represents a MAC operation result of the inputs and the weights,

in presenting x-level weight of a weight unit comprising at least one memory cell among the plurality of memory cells, the at least one memory cell of the weight unit being coupled to a single one of the word lines, and the weight unit receiving a single input of the plurality of inputs via the single one of the word lines, a number of the second signal lines coupled to the same conversion unit is expressed as: Q=2 x −1, x and Q are both positive integers, Q is the number of the second signal lines coupled to the same conversion unit; and

the memory cells are single-level storage cells,

in performing the MAC operation, a plurality of transistors of the local signal line decoder are turned on.

5. The operation method for the memory device according to claim 4 , wherein in performing the MAC operation, a local signal line decoder sums the signal line currents into the global signal line current.

6. The operation method for the memory device according to claim 5 , wherein the conversion unit converts the global signal line current into the output; and

each of the plurality of transistors of the local signal line decoder includes a first terminal coupled to one among the second signal lines, a second terminal coupled to a global signal line and an input of the conversion unit, and a control terminal for receiving a control signal.

7. The operation method for the memory device according to claim 4 , wherein the conversion unit is an analog-to-digital converter (ADC).

8. A memory device comprising:

a memory array including a plurality of memory cells, the memory cells storing a plurality of weights, the memory cells being coupled to a plurality of word lines, a plurality of first signal lines and a plurality of second signal lines, the plurality of memory cells are controlled by the plurality of word lines;

at least one first local signal line decoder coupled to the memory array and at least one first global signal line; and

at least one conversion unit coupled to the at least one first local signal line decoder and the at least one first global signal line,

wherein in presenting x-level weight of a weight unit comprising at least one memory cell among the plurality of memory cells, the at least one memory cell of the weight unit being coupled to a single one of the word lines, and the weight unit receiving a single input of the plurality of inputs via the single one of the word lines, a number of the second signal lines coupled to the same conversion unit is expressed as: Q=2 x −1, x and Q are both positive integers, Q is the number of the second signal lines coupled to the same conversion unit; and

the memory cells are single-level storage cells,

in performing the MAC operation, a plurality of transistors of the local signal line decoder are turned on.

9. The memory device according to claim 8 , wherein

in performing a multiply accumulate (MAC) operation, a plurality of inputs are input into the memory cells via the word lines;

the memory cells output a plurality of cell currents to the second signal lines based on the weights of the memory cells;

the cell currents on each of the second signal lines are summed into a plurality of signal line currents and input into the at least one first local signal line decoder;

the at least one first local signal line decoder sums the signal line currents into a global signal line current; and

the at least one conversion unit converts the global signal line current from the at least one first local signal line decoder into an output, wherein the output represents a MAC operation result of the inputs and the weights.

10. The memory device according to claim 8 , wherein the memory device is a 3D (three-dimension) AND memory device.

11. The memory device according to claim 8 , wherein the at least one first global signal line includes a plurality of first global signal lines and the at least one conversion unit includes a plurality of conversion units, each of the first global signal lines is coupled to each of the conversion units.

12. The memory device according to claim 9 , wherein each of the plurality of first transistors of the at least one first local signal line decoder includes a first terminal coupled to one among the second signal lines, a second terminal coupled to the at least one first global signal line and an input of the at least one conversion unit, and a control terminal for receiving a control signal.

13. The memory device according to claim 8 , wherein the at least one conversion unit is an analog-to-digital converter (ADC).

14. The memory device according to claim 8 , further including at least one second local signal line decoder having a plurality of second transistors, each of the plurality of second transistors of the at least one second local signal line decoder including a first terminal coupled to one among a plurality of third signal lines, a second terminal coupled to at least one second global signal line, and a control terminal for receiving a control signal.