Split read port latch array bit cell
An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.
1. A circuit comprising:
an array of memory bit cells configured to store data arranged as a plurality of rows and a plurality of columns, wherein:
a first portion of the plurality of rows are connected to a first read bit line of a given column of the plurality of columns and not connected to a second read bit line of the given column of the plurality of columns; and
a second portion of the plurality of rows are connected to the second read bit line and not connected to the first read bit line; and
circuitry configured to pre-charge one of the first read bit line and the second read bit line to a power supply reference level and pre-charge the other one of the first read bit line and second read bit line to a ground reference level;
wherein in response to receiving an indication of a first read operation targeting a row of the first portion comprising a first memory bit cell, the array of memory bit cells is configured to convey first data stored in the first memory bit cell to the first read bit line via a first asymmetrical read access circuit.
2. The circuit as recited in claim 1 , wherein:
the first portion of the plurality of rows comprises odd numbered rows of the plurality of rows; and
the second portion of the plurality of rows comprises even numbered rows of the plurality of rows.
3. The circuit as recited in claim 1 , wherein in response to receiving a second read operation targeting a row of the second portion comprising a second memory bit cell, the array of memory bit cells is configured to convey second data stored in the second memory bit cell to the second read bit line via a second asymmetrical read access circuit different from the first asymmetrical read access circuit comprising more p-type transistors than n-type transistors.
4. The circuit as recited in claim 3 , wherein the array of memory bit cells is configured to convey the first data and the second data in a same clock cycle.
5. The circuit as recited in claim 3 , wherein the second asymmetrical read access circuit comprises only p-type transistors.
6. The circuit as recited in claim 1 , wherein the first memory bit cell comprises a different number of transistors of a given type than a second memory bit cell adjacent to the first memory bit cell.
7. The circuit as recited in claim 5 , wherein the circuit further comprises circuitry configured to pre-charge the first read bit line to a power supply reference level and pre-charge the second read bit line to a ground reference level.
8. The circuit as recited in claim 5 , wherein the second asymmetrical read access circuit comprises:
a first p-type transistor configured to receive, on its gate terminal, a complementary value of the data stored by a data storage circuit; and
a second p-type transistor in series with the first p-type transistor configured to:
receive, on its gate terminal, a read word line as the indication of the second read operation; and
receive, on its drain terminal, the second read bit line.
9. A method comprising:
storing data in an array of memory bit cells arranged as a plurality of rows and a plurality of columns, wherein:
a first portion of the plurality of rows are connected to a first read bit line of a given column of the plurality of columns and not connected to a second read bit line of the given column of the plurality of columns; and
a second portion of the plurality of rows are connected to the second read bit line and not connected to the first read bit line; and
pre-charging one of the first read bit line and the second read bit line to a power supply reference level and pre-charging the other one of the first read bit line and second read bit line to a ground reference level;
wherein in response to receiving an indication of a first read operation targeting a row of the first portion comprising a first memory bit cell, conveying first data stored in the first memory bit cell to the first read bit line via a first asymmetrical read access circuit.
10. The method as recited in claim 9 , wherein:
the first portion of the plurality of rows comprises odd numbered rows of the plurality of rows; and
the second portion of the plurality of rows comprises even numbered rows of the plurality of rows.
11. The method as recited in claim 9 , wherein in response to receiving a second read operation targeting a row of the second portion comprising a second memory bit cell, the method further comprises conveying second data stored in the second memory bit cell to the second read bit line via a second asymmetrical read access circuit different from the first asymmetrical read access circuit comprising more p-type transistors than n-type transistors.
12. The method as recited in claim 11 , further comprising conveying, by the array of memory bit cells, the first data and the second data in a same clock cycle.
13. The method as recited in claim 11 , wherein the second asymmetrical read access circuit comprising only p-type transistors.
14. The method as recited in claim 9 , wherein first memory bit cell comprises a different number of transistors of a given type than a second memory bit cell adjacent to the first memory bit cell.