Input/output semiconductor devices

1. A method, comprising:

forming first channel members over a first region of a substrate and second channel members over a second region of the substrate;

forming a first interfacial layer over the first channel members to a first thickness;

forming a second interfacial layer over the second channel members to a second thickness smaller than the first thickness;

forming a first hafnium-containing dielectric layer over the first interfacial layer to a third thickness; and

forming a second hafnium-containing dielectric layer over the second interfacial layer to a fourth thickness greater than the third thickness.

2. The method of claim 1 , wherein the forming of the first hafnium-containing dielectric layer over the first interfacial layer comprises:

depositing the second hafnium-containing dielectric layer over the first interfacial layer in the first region and the second interfacial layer in the second region;

masking the second hafnium-containing dielectric layer in the second region; and

thinning the second hafnium-containing dielectric layer in the first region to form the first hafnium-containing dielectric layer.

3. The method of claim 1 , wherein the first interfacial layer and the second interfacial layer comprises silicon oxide or silicon oxynitride.

4. The method of claim 1 , wherein the first hafnium-containing dielectric layer and the second hafnium-containing dielectric layer comprises hafnium oxide, hafnium zirconium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or hafnium aluminum oxide.

5. The method of claim 1 ,

wherein the first thickness is between about 15 Å and about 35 Å,

wherein the second thickness is between about 5 Å and about 15 Å.

6. The method of claim 1 ,

wherein the third thickness is smaller than about 10 Å,

wherein the fourth thickness is between about 14 Å and about 18 Å.

7. The method of claim 2 , wherein the thinning of the second hafnium-containing dielectric layer comprises:

using the second hafnium-containing dielectric layer as an etch stop layer.

8. A method, comprising:

forming first nanostructures over a first region of a substrate and second nanostructures over a second region of the substrate;

forming a first interfacial layer over the first nanostructures and the second nanostructures to a first thickness;

selectively removing the first interfacial layer over the second nanostructures;

after the selectively removing, forming a second interfacial layer over the second nanostructures to a second thickness smaller than the first thickness;

forming a first gate dielectric layer over the first interfacial layer and the second interfacial layer to a third thickness; and

selectively thinning the first gate dielectric layer over the first interfacial layer to form a second gate dielectric layer having a fourth thickness smaller than the third thickness.

9. The method of claim 8 , wherein the selectively removing comprises:

forming a first mask layer over the first region while the second region is exposed.

10. The method of claim 9 , wherein the first mask layer comprises a bottom antireflective coating (BARC) layer.

11. The method of claim 8 , wherein the selectively thinning comprises:

forming a second mask layer over the second region while the first region is exposed.

12. The method of claim 8 ,

wherein the first nanostructures are vertically stacked one over another,

wherein the second nanostructures are vertically stacked one over another.

13. The method of claim 8 ,

wherein the first thickness is between about 15 Å and about 35 Å,

wherein the second thickness is between about 5 Å and about 15 Å.

14. The method of claim 8 ,

wherein the third thickness is smaller than about 10 Å,

wherein the fourth thickness is between about 14 Å and about 18 Å.

15. The method of claim 8 , wherein the first gate dielectric layer and the second gate dielectric layer comprise hafnium oxide, hafnium zirconium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, or a combination thereof.

16. A method, comprising:

forming first nanostructures over a first region of a substrate and second nanostructures over a second region of the substrate;

selectively forming a first interfacial layer over the first nanostructures to a first thickness;

selectively forming a second interfacial layer over the second nanostructures to a second thickness smaller than the first thickness;

selectively forming a first gate dielectric layer over the second interfacial layer to a third thickness; and

selectively forming a second gate dielectric layer over the first interfacial layer to a fourth thickness smaller than the third thickness.

17. The method of claim 16 , wherein a composition of the first gate dielectric layer is identical to a composition of the second gate dielectric layer.

18. The method of claim 16 , further comprising:

depositing an n-dipole layer over the first gate dielectric layer and the second gate dielectric layer;

selectively removing the n-dipole layer over the first gate dielectric layer; and

after the selectively removing, depositing a gate electrode layer over the n-dipole layer in the first region and the first gate dielectric layer in the second region.

19. The method of claim 18 , wherein the n-dipole layer comprises lanthanum oxide, magnesium oxide, or yttrium oxide.

20. The method of claim 18 , wherein the gate electrode layer comprises titanium nitride, titanium silicon nitride, titanium aluminum nitride, tungsten carbonitride, titanium aluminum carbide, titanium aluminide.